ADC (Analog Digital Converter)

group group_hal_impl_adc

Features

The CAT1A/CAT2 (PMG/PSoC 4/PSoC 6) ADC supports the following features:

  • Resolution: 12 bit

  • Only CYHAL_POWER_LEVEL_DEFAULT and CYHAL_POWER_LEVEL_OFF are defined. The default power level will automatically adjust based on smple rate.

  • Average counts: 2, 4, 8, 16, 32, 64, 128, 256

  • Up to four unique acquisition times.

  • DMA-based transfer when using cyhal_adc_read_async. When using cyhal_adc_read_async_uv, only interrupt-driven software copy is supported.

After initializing the ADC or changing the reference or bypass selection, it may be necessary to wait up to 210 us for the reference buffer to settle. See the architecture TRM (Analog Subsystem -> SAR ADC -> Architecture -> SARREF) for device specific guidance.

Unnamed Group

CYHAL_ADC_AVG_MODE_SEQUENTIAL

Convert all samples to be averaged back to back, before proceeding to the next channel.

Interconnect

In PSoC each ADC has a single input trigger which, when activated, will initiate an ADC scan. Each ADC also has an output trigger which will be activated when a scan is completed. This is the default behavior.