System Power Management¶
Switching the System into Ultra Low Power
Before switching into system Ultra Low Power mode, ensure that the device meets the requirements below:
The core regulator voltage is set to 0.9 V (nominal) and the following limitations must be meet:
The maximum operating frequency for all Clk_HF paths must not exceed 50* MHz
The maximum operating frequency for peripheral and slow clock must not exceed 25* MHz.
The total current consumption must be less than or equal to 20* mA
Flash write operations are prohibited. Flash is Read-only in this mode.
* - Numbers shown are approximate and real limit values may be different because they are device specific. You should refer to the device datasheet for exact values of maximum frequency and current in system ULP mode.