SPI (Serial Peripheral Interface)

group group_hal_spi

High level interface for interacting with the Serial Peripheral Interface (SPI).

The SPI protocol is a synchronous serial interface protocol. Devices operate in either master or slave mode. The master initiates the data transfer.

Motorola SPI modes 0, 1, 2, and 3 are supported, with either MSB or LSB first. The operating mode and data frame size can be configured via cyhal_spi_cfg_t.

Features

  • Supports master and slave functionality.

  • Supports Motorola modes - 0, 1, 2 and 3 - cyhal_spi_mode_t

  • MSb or LSb first shift direction - cyhal_spi_mode_t

  • Master supports up to four slave select lines

  • Supports data frame size of 8 or 16 bits

  • Configurable interrupt and callback assignment on SPI events: Data transfer to FIFO complete, Transfer complete and Transmission error - cyhal_spi_event_t

  • Supports changing baud rate of the transaction in run time.

  • Provides functions to send/receive a single byte or block of data.

Quick Start

Initialise a SPI master or slave interface using cyhal_spi_init() and provide the SPI pins (mosi, miso, sclk, ssel), number of bits per frame (data_bits) and SPI Motorola mode. The data rate can be set using cyhal_spi_set_frequency().

See

Code snippets for code snippets to send or receive the data.

Code snippets

Snippet 1: SPI Master - Single byte transfer operation (Read and Write)

The following code snippet initializes an SPI Master interface using the cyhal_spi_init(). The data rate of transfer is set using cyhal_spi_set_frequency(). The code snippet shows how to transfer a single byte of data using cyhal_spi_send() and cyhal_spi_recv().

    cy_rslt_t   rslt;
    cyhal_spi_t mSPI;
    uint32_t    spi_master_frequency = 1000000;
    uint32_t    transmit_data        = 0x01;
    uint32_t    receive_data;

    // Configuring the  SPI master:  Specify the SPI interface pins, frame size, SPI Motorola mode
    // and master mode
    rslt = cyhal_spi_init(&mSPI, CYBSP_SPI_MOSI, CYBSP_SPI_MISO, CYBSP_SPI_CLK, CYBSP_SPI_CS, NULL,
                          8, CYHAL_SPI_MODE_00_MSB, false);

    // Set the data rate to 1 Mbps
    rslt = cyhal_spi_set_frequency(&mSPI, spi_master_frequency);

    // Transfer one byte of data to the slave.
    if (CY_RSLT_SUCCESS == cyhal_spi_send(&mSPI, transmit_data))
    {
        // Receives one byte of data from the slave by transmiting a dummy byte 0xFF.
        if (CY_RSLT_SUCCESS == cyhal_spi_recv(&mSPI, &receive_data))
        {
            // Transfer Complete and successful
        }
    }

Snippet 2: SPI Slave - Single byte transfer operation (Read and Write)

The following code snippet initializes an SPI Slave interface using the cyhal_spi_init(). The data rate of transfer is set using cyhal_spi_set_frequency. The code snippet shows how to transfer a single byte of data using cyhal_spi_send() and cyhal_spi_recv.

    cy_rslt_t   rslt;
    cyhal_spi_t sSPI;
    uint32_t    spi_slave_frequency = 1000000;
    uint32_t    transmit_data       = 1;
    uint32_t    receive_data;

    // Configuring the  SPI slave:  Specify the SPI interface pins, frame size, SPI Motorola mode
    // and slave mode
    rslt = cyhal_spi_init(&sSPI, CYBSP_SPI_MOSI, CYBSP_SPI_MISO, CYBSP_SPI_CLK, CYBSP_SPI_CS, NULL,
                          8, CYHAL_SPI_MODE_00_MSB, true);

    // Set the data rate to 1 Mbps
    rslt = cyhal_spi_set_frequency(&sSPI, spi_slave_frequency);

    // Place a byte in the TX FIFO to be read by the master
    if (CY_RSLT_SUCCESS == cyhal_spi_send(&sSPI, transmit_data))
    {
        // Get a received value out of the SPI receive buffer. This API Blocks until a value is
        // available
        if (CY_RSLT_SUCCESS == cyhal_spi_recv(&sSPI, &receive_data))
        {
            // Transfer successful
        }
    }

Snippet 3: SPI Block Data transfer

The following snippet sends and receives an array of data in a single SPI transaction using cyhal_spi_transfer(). The example uses SPI master to transmit 5 bytes of data and receive 5 bytes of data in a single transaction.

    cy_rslt_t   rslt;
    cyhal_spi_t mSPI;
    uint32_t    spi_frequency    = 1000000;
    uint8_t     transmit_data[5] = { 0x1, 0x2, 0x3, 0x4, 0x5 };
    uint8_t     receive_data[5];

    // BSP-1637 workaround
    memset(&mSPI, 0, sizeof(mSPI));

    // Configuring the  SPI interface:  Specify the SPI interface pins, frame size, SPI Motorola
    // mode and master/slave mode
    rslt = cyhal_spi_init(&mSPI, CYBSP_SPI_MOSI, CYBSP_SPI_MISO, CYBSP_SPI_CLK, CYBSP_SPI_CS, NULL,
                          8, CYHAL_SPI_MODE_00_MSB, false);

    // Set the data rate to 1 Mbps
    rslt = cyhal_spi_set_frequency(&mSPI, spi_frequency);

    // Master: Starts a data transfer. Slave: Prepares the slave for data transfer. It is a blocking
    // function
    if (CY_RSLT_SUCCESS == cyhal_spi_transfer(&mSPI, transmit_data, 5u, receive_data, 5u, 0xFF))
    {
        // Transfer Complete
    }

Snippet 4: Interrupts on SPI events

SPI interrupt events ( cyhal_spi_event_t) can be mapped to an interrupt and assigned to a callback function. The callback function needs to be first registered and then the event needs to be enabled. The following snippet initialises a SPI master to perform a block transfer using cyhal_spi_transfer_async(). This is a non-blocking function. A callback function is registered using cyhal_spi_register_callback to notify whenever the SPI transfer is complete.


void spi_interrupt_callback(void* arg, cyhal_spi_event_t event)
{
    (void)arg;
    if ((event & CYHAL_SPI_IRQ_DONE) != 0u)
    {
        // Transmission is complete. Handle Event
    }
}


void snippet_cyhal_interrupt_callback_events(void)
{
    cy_rslt_t   rslt;
    cyhal_spi_t mSPI;
    uint32_t    spi_frequency = 1000000;
    uint32_t    rx_transfer_count = 5, tx_transfer_count = 5;
    uint8_t     receive_data[5];
    uint8_t     transmit_data[5] = { 0x1, 0x2, 0x3, 0x4, 0x5 };

    // Configuring the  SPI interface:  Specify the SPI interface pins, frame size, SPI Motorola
    // mode and master/slave mode
    rslt = cyhal_spi_init(&mSPI, CYBSP_SPI_MOSI, CYBSP_SPI_MISO, CYBSP_SPI_CLK, CYBSP_SPI_CS, NULL,
                          8, CYHAL_SPI_MODE_00_MSB, false);
    CY_ASSERT(CY_RSLT_SUCCESS == rslt);

    // Set the data rate to 1 Mbps
    rslt = cyhal_spi_set_frequency(&mSPI, spi_frequency);
    CY_ASSERT(CY_RSLT_SUCCESS == rslt);

    // Register a callback function to be called when the interrupt fires
    cyhal_spi_register_callback(&mSPI, (cyhal_spi_event_callback_t)spi_interrupt_callback, NULL);

    // Enable the events that will trigger the call back function
    cyhal_spi_enable_event(&mSPI, CYHAL_SPI_IRQ_DONE, 3, true);

    // Master: Initiates a data transfer. Slave: Prepares the slave for data transfer. It is a
    // non-blocking function
    if (CY_RSLT_SUCCESS ==
        cyhal_spi_transfer_async(&mSPI, transmit_data, rx_transfer_count, receive_data,
                                 tx_transfer_count))
    {
        // SPI Master: Transfer started. SPI Slave: Prepares for data transfer
    }
}

More Information

  • mtb-example-psoc6-spi-master: This example project demonstrates use of SPI (HAL) resource in PSoC® 6 MCU in Master mode to write data to an SPI slave.

Defines

cyhal_spi_frequency

Compatibility define for cyhal_spi_set_frequency.

CYHAL_SPI_MODE_FLAG_LSB

Flag for SPI cyhal_spi_mode_t values indicating that the LSB is sent first.

CYHAL_SPI_MODE_FLAG_CPHA

Flag for SPI cyhal_spi_mode_t values indicating that the CPHA=1.

CYHAL_SPI_MODE_FLAG_CPOL

Flag for SPI cyhal_spi_mode_t values indicating that the CPOL=1.

CYHAL_SPI_MODE(cpol, cpha, lsb)

Creates a cyhal_spi_mode_t value given the cpol, cpha, lsb values.

Typedefs

typedef void (*cyhal_spi_event_callback_t)(void *callback_arg, cyhal_spi_event_t event)

Handler for SPI interrupts.

Enums

enum cyhal_spi_event_t

cyhal_spi_event_t: SPI interrupt triggers.

Values:

enumerator CYHAL_SPI_IRQ_DATA_IN_FIFO

All transfer data has been moved into data FIFO.

enumerator CYHAL_SPI_IRQ_DONE

Transfer complete.

enumerator CYHAL_SPI_IRQ_ERROR

An error occurred while transferring data.

enum cyhal_spi_ssel_polarity_t

cyhal_spi_ssel_polarity_t: SPI Slave Select polarity.

Values:

enumerator CYHAL_SPI_SSEL_ACTIVE_LOW

SSEL signal is active low.

enumerator CYHAL_SPI_SSEL_ACTIVE_HIGH

SSEL signal is active high.

enum cyhal_spi_mode_t

cyhal_spi_mode_t: SPI operating modes.

Values:

enumerator CYHAL_SPI_MODE_00_MSB

Standard motorola SPI CPOL=0, CPHA=0 with MSB first operation.

enumerator CYHAL_SPI_MODE_00_LSB

Standard motorola SPI CPOL=0, CPHA=0 with LSB first operation.

enumerator CYHAL_SPI_MODE_01_MSB

Standard motorola SPI CPOL=0, CPHA=1 with MSB first operation.

enumerator CYHAL_SPI_MODE_01_LSB

Standard motorola SPI CPOL=0, CPHA=1 with LSB first operation.

enumerator CYHAL_SPI_MODE_10_MSB

Standard motorola SPI CPOL=1, CPHA=0 with MSB first operation.

enumerator CYHAL_SPI_MODE_10_LSB

Standard motorola SPI CPOL=1, CPHA=0 with LSB first operation.

enumerator CYHAL_SPI_MODE_11_MSB

Standard motorola SPI CPOL=1, CPHA=1 with MSB first operation.

enumerator CYHAL_SPI_MODE_11_LSB

Standard motorola SPI CPOL=1, CPHA=1 with LSB first operation.

enum cyhal_spi_fifo_type_t

cyhal_spi_fifo_type_t: SPI FIFO type.

Values:

enumerator CYHAL_SPI_FIFO_RX

Set RX FIFO level.

enumerator CYHAL_SPI_FIFO_TX

Set TX FIFO level.

enum cyhal_spi_output_t

cyhal_spi_output_t: Enum of possible output signals from an SPI.

Values:

enumerator CYHAL_SPI_OUTPUT_TRIGGER_RX_FIFO_LEVEL_REACHED

Output the RX FIFO signal which is triggered when the receive FIFO has more entries than the configured level.

enumerator CYHAL_SPI_OUTPUT_TRIGGER_TX_FIFO_LEVEL_REACHED

Output the TX FIFO signal which is triggered when the transmit FIFO has less entries than the configured level.

Functions

cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, cyhal_gpio_t sclk, cyhal_gpio_t ssel, const cyhal_clock_t *clk, uint8_t bits, cyhal_spi_mode_t mode, bool is_slave)

Initialize the SPI peripheral.

Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral

note

At least MOSI or MISO pin should be non-NC

note

At least MOSI or MISO pin should be non-NC

note

This pin cannot be NC

note

Provided pin will be configured for CYHAL_SPI_SSEL_ACTIVE_LOW polarity and set as active. This can be changed (as well as additional ssel pins can be added) by cyhal_spi_slave_select_config and cyhal_spi_select_active_ssel functions. This pin can be NC.

note

bits should be 8 or 16

Return

The status of the init request

Parameters
  • [out] obj: Pointer to a SPI object. The caller must allocate the memory for this object but the init function will initialize its contents.

  • [in] mosi: The pin to use for MOSI

Parameters
  • [in] miso: The pin to use for MISO

Parameters
  • [in] sclk: The pin to use for SCLK

Parameters
  • [in] ssel: The pin to use for SSEL

Parameters
  • [in] clk: The clock to use can be shared, if not provided a new clock will be allocated

  • [in] bits: The number of bits per frame

Parameters
  • [in] mode: The SPI mode (clock polarity, phase, and shift direction)

  • [in] is_slave: false for master mode or true for slave mode operation

void cyhal_spi_free(cyhal_spi_t *obj)

Release a SPI object.

Return the peripheral, pins and clock owned by the SPI object to their reset state

Parameters
  • [inout] obj: The SPI object to deinitialize

cy_rslt_t cyhal_spi_set_frequency(cyhal_spi_t *obj, uint32_t hz)

Set the SPI baud rate.

Actual frequency may differ from the desired frequency due to available dividers and bus clock Configures the SPI peripheral’s baud rate

Return

The status of the set_frequency request

Parameters
  • [inout] obj: The SPI object to configure

  • [in] hz: The baud rate in Hz

cy_rslt_t cyhal_spi_slave_select_config(cyhal_spi_t *obj, cyhal_gpio_t ssel, cyhal_spi_ssel_polarity_t polarity)

Configures provided ssel pin to work as SPI slave select with specified polarity.

Multiple pins can be configured as SPI slave select pins. Please refer to device datasheet for details. Switching between configured slave select pins is done by cyhal_spi_select_active_ssel function. Unless modified with this function, the SSEL pin provided as part of cyhal_spi_init is the default.

Return

The status of ssel pin configuration

Parameters
  • [in] obj: The SPI object to add slave select for

  • [in] ssel: Slave select pin to be added

  • [in] polarity: Polarity of slave select

cy_rslt_t cyhal_spi_select_active_ssel(cyhal_spi_t *obj, cyhal_gpio_t ssel)

Selects an active slave select line from one of available.

This function is applicable for the master and slave. SSEL pin should be configured by cyhal_spi_slave_select_config or cyhal_spi_init functions prior to selecting it as active. The active slave select line will automatically be toggled as part of any transfer.

Return

CY_RSLT_SUCCESS if slave select was switched successfully, otherwise - CYHAL_SPI_RSLT_ERR_CANNOT_SWITCH_SSEL

Parameters
  • [in] obj: The SPI object for switching

  • [in] ssel: Slave select pin to be set as active

cy_rslt_t cyhal_spi_recv(cyhal_spi_t *obj, uint32_t *value)

Synchronously get a received value out of the SPI receive buffer.

In Master mode - transmits fill-in value and read the data from RxFifo In Slave mode - Blocks until a value is available

note

  • In Master mode, MISO pin required to be non-NC for this API to operate

  • In Slave mode, MOSI pin required to be non-NC for this API to operate

Return

The status of the read request

Parameters
  • [in] obj: The SPI peripheral to read

  • [in] value: The value received

cy_rslt_t cyhal_spi_send(cyhal_spi_t *obj, uint32_t value)

Synchronously send a byte out.

In Master mode transmits value to slave and read/drop a value from the RxFifo. In Slave mode writes a value to TxFifo

note

  • In Master mode, MOSI pin required to be non-NC for this API to operate

  • In Slave mode, MISO pin required to be non-NC for this API to operate

Return

The status of the write request

Parameters
  • [in] obj: The SPI peripheral to use for sending

  • [in] value: The value to send

cy_rslt_t cyhal_spi_transfer(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length, uint8_t write_fill)

Synchronously Write a block out and receive a value.

The total number of bytes sent and received will be the maximum of tx_length and rx_length. The bytes written will be padded (at the end) with the value given by write_fill.

This function will block for the duration of the transfer. cyhal_spi_transfer_async can be used for non-blocking transfers.

note

Both MOSI and MISO pins required to be non-NC for this API to operate

Return

The status of the transfer request

Parameters
  • [in] obj: The SPI peripheral to use for sending

  • [in] tx: Pointer to the byte-array of data to write to the device

  • [inout] tx_length: Number of bytes to write, updated with the number actually written

  • [out] rx: Pointer to the byte-array of data to read from the device

  • [inout] rx_length: Number of bytes to read, updated with the number actually read

  • [in] write_fill: Default data transmitted while performing a read

cy_rslt_t cyhal_spi_transfer_async(cyhal_spi_t *obj, const uint8_t *tx, size_t tx_length, uint8_t *rx, size_t rx_length)

Start an asynchronous SPI transfer.

This will transfer rx_length bytes into the buffer pointed to by rx, while simultaneously transfering tx_length bytes of data from the buffer pointed to by tx, both in the background. When the transfer is complete, the CYHAL_SPI_IRQ_DONE event will be raised. See cyhal_spi_register_callback and cyhal_spi_enable_event.

note

For blocking transfers cyhal_spi_transfer can be used.

note

Both MOSI and MISO pins required to be non-NC for this API to operate

Return

The status of the transfer_async request

Parameters
  • [in] obj: The SPI object that holds the transfer information

  • [in] tx: The transmit buffer

  • [inout] tx_length: The number of bytes to transmit

  • [out] rx: The receive buffer

  • [inout] rx_length: The number of bytes to receive

bool cyhal_spi_is_busy(cyhal_spi_t *obj)

Checks if the specified SPI peripheral is in use.

Return

Indication of whether the SPI is still transmitting

Parameters
  • [in] obj: The SPI peripheral to check

cy_rslt_t cyhal_spi_abort_async(cyhal_spi_t *obj)

Abort an SPI transfer.

Return

The status of the abort_async request

Parameters
  • [in] obj: The SPI peripheral to stop

void cyhal_spi_register_callback(cyhal_spi_t *obj, cyhal_spi_event_callback_t callback, void *callback_arg)

Register a SPI callback handler.

This function will be called when one of the events enabled by cyhal_spi_enable_event occurs.

Parameters
  • [in] obj: The SPI object

  • [in] callback: The callback handler which will be invoked when the interrupt fires

  • [in] callback_arg: Generic argument that will be provided to the callback when called

void cyhal_spi_enable_event(cyhal_spi_t *obj, cyhal_spi_event_t event, uint8_t intr_priority, bool enable)

Configure SPI interrupt.

This function is used for word-approach

When an enabled event occurs, the function specified by cyhal_spi_register_callback will be called.

Parameters
  • [in] obj: The SPI object

  • [in] event: The SPI event type

  • [in] intr_priority: The priority for NVIC interrupt events

  • [in] enable: True to turn on interrupts, False to turn off

cy_rslt_t cyhal_spi_set_fifo_level(cyhal_spi_t *obj, cyhal_spi_fifo_type_t type, uint16_t level)

Sets a threshold level for a FIFO that will generate an interrupt and a trigger output.

The RX FIFO interrupt and trigger will be activated when the receive FIFO has more entries than the threshold. The TX FIFO interrupt and trigger will be activated when the transmit FIFO has less entries than the threshold.

Return

The status of the level set

Parameters
  • [in] obj: The SPI object

  • [in] type: FIFO type to set level for

  • [in] level: Level threshold to set

cy_rslt_t cyhal_spi_enable_output(cyhal_spi_t *obj, cyhal_spi_output_t output, cyhal_source_t *source)

Enables the specified output signal from an SPI.

Return

The status of the output enable

Parameters
  • [in] obj: The SPI object

  • [in] output: Which output signal to enable

  • [out] source: Pointer to user-allocated source signal object which will be initialized by enable_output. source should be passed to (dis)connect_digital functions to (dis)connect the associated endpoints.

cy_rslt_t cyhal_spi_disable_output(cyhal_spi_t *obj, cyhal_spi_output_t output)

Disables the specified output signal from an SPI.

Return

The status of the output disable

Parameters
  • [in] obj: The SPI object

  • [in] output: Which output signal to disable

struct cyhal_spi_cfg_t
#include <cyhal_spi.h>

Initial SPI configuration.

Public Members

cyhal_spi_mode_t mode

The operating mode.

uint8_t data_bits

The number of bits per transfer.

bool is_slave

Whether the peripheral is operating as slave or master.