# CTB (Continuous Time Block)¶

group group_ctb

This driver provides API functions to configure and use the analog CTB.

The functions and other declarations used in this driver are in cy_ctb.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.

The CTB comprises two identical opamps, a switch routing matrix, and a sample and hold (SH) circuit. The high level features are:

• Two highly configurable opamps

• Each opamp has programmable power and output drive strength

• Each opamp can be configured as a voltage follower using internal routing

• Each opamp can be configured as a comparator with optional 10 mV hysteresis

• Flexible input and output routing

• Works as a buffer or amplifier for SAR ADC inputs

• Works as a buffer, amplifier, or sample and hold (SH) for the CTDAC output

• Can operate in Deep Sleep power mode

Each opamp, marked OA0 and OA1, has one input and three output stages, all of which share the common input stage. Note that only one output stage can be selected at a time. The output stage can operate as a low-drive strength opamp for internal connections (1X), a high-drive strength opamp for driving a device pin (10X), or a comparator.

Using the switching matrix, the opamp inputs and outputs can be connected to dedicated general-purpose I/Os or other internal analog blocks. See the device datasheet for the dedicated CTB port.

Initialization and Enable

Before enabling the CTB, set up any external components (such as resistors) that are needed for the design and initialize SysAnalog (System Analog Reference Block) by calling Cy_SysAnalog_Init and Cy_SysAnalog_Enable functions. To configure the entire hardware CTB block, call Cy_CTB_Init. The base address of the CTB hardware can be found in the device specific header file. Alternatively, to configure only one opamp without any routing, call Cy_CTB_OpampInit. The driver also provides a Cy_CTB_FastInit function for fast and easy initialization of the CTB based on commonly used configurations. They are pre-defined in the driver as:

Opamp0

Opamp1

After initialization, call Cy_CTB_Enable to enable the hardware.

Input/Output Connections

The CTB has internal switches to support flexible input and output routing. If these switches have not been configured during initialization, call Cy_CTB_SetAnalogSwitch to make the input and output connections.

    /* Scenario: OA0 has been configured as an opamp with 10x output drive using the
* pre-defined Cy_CTB_Fast_Opamp0_Opamp10x configuration. The 10x output has
* a dedicated connection to Pin 9.2.
*
* Call SetAnalogSwitch to route the non-inverting input of OA0 to Pin 9.0
* and the inverting input to Pin 9.1.
*
* Note that the CTB port may vary based on device. */

/* Select OA0 switch register. */
cy_en_ctb_switch_register_sel_t switchSelect = CY_CTB_SWITCH_OA0_SW;

/* Select two switches for Pin 0 and Pin 1 of the CTB port. */
uint32_t switchMask = CY_CTB_SW_OA0_POS_PIN0_MASK | CY_CTB_SW_OA0_NEG_PIN1_MASK;

/* Set the state of the switches to closed */
cy_en_ctb_switch_state_t state = CY_CTB_SWITCH_CLOSE;

Cy_CTB_SetAnalogSwitch(CTBM0, switchSelect, switchMask, state);

As shown in the CTB switch diagram, the 10x output of OA0 and OA1 have dedicated connections to Pin 2 and Pin 3, respectively, of the CTB port. If different output connections are required, the other CTB switches and/or AMUXBUX A/B switches can be used.

Comparator Mode

Each opamp can be configured as a comparator. Note that when used as a comparator, the hardware shuts down the 1X and 10X output drivers. Specific to the comparator mode, there is an optional 10 mV input hysteresis and configurable edge detection interrupt handling.

• Negative input terminal: This input is usually connected to the reference voltage.

• Positive input terminal: This input is usually connected to the voltage that is being compared.

• Comparator digital output: This output goes high when the positive input voltage is greater than the negative input voltage.

The comparator output can be routed to a pin or other components using HSIOM or trigger muxes.

    /* Scenario: OA0 and OA1 of the CTB have been configured as comparators.
* Route the digital outputs of comparator 0 and 1 to
* P9.2 and P9.3, respectively, using HSIOM. */
Cy_GPIO_Pin_FastInit(GPIO_PRT9, 2UL, CY_GPIO_DM_STRONG_IN_OFF, 0UL, P9_2_PASS_DSI_CTB_CMP0);

Cy_GPIO_Pin_FastInit(GPIO_PRT9, 3UL, CY_GPIO_DM_STRONG_IN_OFF, 0UL, P9_3_PASS_DSI_CTB_CMP1);


Handling interrupts

The comparator output is connected to an edge detector block, which is used to detect the edge (rising, falling, both, or disabled) for interrupt generation.

The following code snippet demonstrates how to implement a routine to handle the interrupt. The routine gets called when any comparator on the device generates an interrupt.


/* ISR function to handle the global CTB interrupt. */
void Comparator_Interrupt(void)
{
uint32_t intrStatus;

/* Get the interrupt status for both comparators of a specific CTB instance on the device. */
intrStatus = Cy_CTB_GetInterruptStatus(CTBM0, CY_CTB_OPAMP_BOTH);

/* Clear both comparator interrupts so that subsequent interrupts can be handled. */
Cy_CTB_ClearInterrupt(CTBM0, CY_CTB_OPAMP_BOTH);

if (CY_CTB_OPAMP_0 == (intrStatus & CY_CTB_OPAMP_0))
{
/* Do something when comparator 0 interrupt occurs. */
}

if (CY_CTB_OPAMP_1 == (intrStatus & CY_CTB_OPAMP_1))
{
/* Do something when comparator 1 interrupt occurs. */
}
}

The following code snippet demonstrates how to configure and enable the interrupt.


/* Scenario: Configure and enable the CTB compartor interrupt. */

const cy_stc_sysint_t CTB_IRQ_cfg = {
#if (CY_CPU_CORTEX_M0P)
/* .intrSrc         = */ NvicMux3_IRQn,             /* CM0+ interrupt is NVIC #3 */
/* .cm0pSrc         = */ pass_interrupt_ctbs_IRQn,  /* Source of NVIC #3 is the global CTB interrupt */
/* .intrPriority    = */ 7UL                        /* Interrupt priority is 7 */
#else
/* .intrSrc         = */ pass_interrupt_ctbs_IRQn,  /* Interrupt source is the global CTB interrupt */
/* .intrPriority    = */ 7UL                        /* Interrupt priority is 7 */
#endif
};

/* Initialize the interrupt with vector at Comparator_Interrupt(). */
(void)Cy_SysInt_Init(&CTB_IRQ_cfg, Comparator_Interrupt);

/* Enable the interrupt. */
NVIC_EnableIRQ(CTB_IRQ_cfg.intrSrc);


Opamp Input and Output Range

The input range of the opamp can be rail-to-rail if the charge pump is enabled. Without the charge pump, the input range is 0 V to VDDA - 1.5 V. The output range of the opamp is typically 0.2 V to VDDA - 0.2 V and will depend on the load. See the device datasheet for more detail.

 Charge Pump Input Range Output Range Enabled 0 V to VDDA 0.2 V to VDDA - 0.2 V Disabled 0 V to VDDA - 1.5 V 0.2 V to VDDA - 0.2 V

Sample and Hold Mode

The CTB has a sample and hold (SH) circuit at the non-inverting input of Opamp0. The circuit includes a hold capacitor, Chold, with a firmware controlled switch, CHD. Sampling and holding the source voltage is performed by closing and opening appropriate switches in the CTB using firmware. If the SH circuit is used for the CTDAC, the Cy_CTB_DACSampleAndHold function should be called.

Configuration Dependencies

The CTB relies on other blocks to function properly. The dependencies are documented here.

Charge Pump Configuration

Each opamp of the CTB has a charge pump that when enabled increases the input range to the supply rails. When disabled, the opamp input range is 0 - VDDA - 1.5 V. When enabled, the pump requires a clock. Call the Cy_CTB_SetPumpClkSource function in the SysAnalog (System Analog Reference Block) driver to set the clock source for all CTBs. This clock can come from one of two sources:

1. A dedicated clock divider from one of the CLK_PATH in the SRSS

Call the following functions to configure the pump clock from the SRSS:

    /* Scenario: Use a 24 Mhz clock from the SRSS for the charge pump clock. */

/* Set the source to clock Path 0, which has been configured for 100 MHz FLL. */
Cy_SysClk_ClkPumpSetSource(CY_SYSCLK_PUMP_IN_CLKPATH0);

/* Divide the 100 Mhz by 4. */
Cy_SysClk_ClkPumpSetDivider(CY_SYSCLK_PUMP_DIV_4);
Cy_SysClk_ClkPumpEnable();

/* Select the source for the pump clock to be from the SRSS. */
Cy_CTB_SetPumpClkSource(PASS, CY_CTB_CLK_PUMP_SRSS);


2. One of the Peri Clock dividers

Call the following functions to configure a Peri Clock divider as the pump clock:

    /* Scenario: Use a 25 Mhz clock from the PeriClk dividers for the charge pump clock. */
uint32_t dividerNum = 1UL;
uint32_t dividerValue = 1UL;

/* Use the 8-bit divider type and divider number 1 from the PeriClk, which has been configured for 50 MHz. */
Cy_SysClk_PeriphAssignDivider(PCLK_PASS_CLOCK_PUMP_PERI, CY_SYSCLK_DIV_8_BIT, dividerNum);

/* Divide the 50 MHz PeriClk by 2 (dividerValue + 1). */
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, dividerNum, dividerValue);
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, dividerNum);

/* Select the source for the pump clock to be from the PeriClk dividers. */
Cy_CTB_SetPumpClkSource(PASS, CY_CTB_CLK_PUMP_PERI);

When the charge pump is enabled, the clock frequency should be set as follows:

 Opamp Power Level Pump Clock Freq Low or Medium 8 - 24 MHz High 24 MHz

The High power level of the opamp requires a 24 MHz pump clock. In Deep Sleep mode, all high frequency clocks are disabled and the charge pump will be disabled.

note

The same pump clock is used by all opamps on the device. Be aware of this when configuring different opamps to different power levels.

Reference Current Configurations

The CTB uses two reference current generators, IPTAT and IZTAT, from the AREF block (see SysAnalog (System Analog Reference Block) driver). The IPTAT current is used to trim the slope of the opamp offset across temperature. The AREF must be initialized and enabled for the CTB to function properly.

If the CTB is configured to operate in Deep Sleep mode, the appropriate reference current generators from the AREF block must be enabled in Deep Sleep. When waking up from Deep Sleep, the AREF block has a wakeup time that must be considered. Note that configurations in the AREF block are chip wide and affect all CTBs on the device.

The following reference current configurations are supported:

 Reference Current Level Supported Mode Input Range 1 uA Active/Low Power Rail-to-Rail (charge pump enabled) 1 uA Active/Low Power/Deep Sleep 0 - VDDA-1.5 V (charge pump disabled) 100 nA Active/Low Power/Deep Sleep 0 - VDDA-1.5 V (charge pump disabled)

The first configuration provides low offset and drift with maximum input range while consuming the most current. For Deep Sleep operation, use the other two configurations with the charge pump disabled. For ultra low power, use the 100 nA current level. To configure the opamps to operate in one of these options, call Cy_CTB_SetCurrentMode.

Sample and Hold Switch Control

If you are using rev-08 of the CY8CKIT-062, the following eight switches in the CTB are enabled by the CTDAC IP block:

• COS, CA0, CHD, CH6, COB, COR, CRS, and CRD

On the rev-08 board, if any of the above switches are used, you must call Cy_CTDAC_Enable to enable these switches.

Additionally, on the rev-08 board, if any of the switches are used in Deep Sleep mode, the CTDAC must also be configured to operate in Deep Sleep (see Cy_CTDAC_SetDeepSleepMode).

In later revisions of the board, the switches are enabled by the CTB block so calls to the CTDAC IP block are not necessary.

More Information

Refer to technical reference manual (TRM) and the device datasheet.

Changelog

 Version Changes Reason for Change 2.0 Added new pump clock source. New silicon family support. The analog routing switches are opening on power down. A FW workaround for possible side-effects of the weak pull-ups at OpAmps terminals in PASS6Av2. 1.20 Fixed the Cy_CTB_OpampInit function to do not affect another OpAmp instance. Bug fixing. 1.10.3 Minor documentation updates. Documentation enhancement. 1.10.2 The Cy_CTB_Init function description is expanded with a clarification note. Documentation enhancement based on a usability feedback. 1.10.1 Added header guard CY_IP_MXS40PASS to the source file. To enable the PDL compilation with wounded out IP blocks. 1.10 Flattened the organization of the driver source code into the single source directory and the single include directory. Driver library directory-structure simplification. Added register access layer. Use register access macros instead of direct register access using dereferenced pointers. Makes register access device-independent, so that the PDL does not need to be recompiled for each supported part number. 1.0 Initial version