CTDAC (Continuous Time Digital to Analog Converter)

group group_ctdac

The CTDAC driver provides APIs to configure the 12-bit Continuous-Time DAC.

The functions and other declarations used in this driver are in cy_ctdac.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.

  • 12-bit continuous time output

  • 2 us settling time for a 25 pF load when output buffered through Opamp0 of CTB

  • Can be enabled in Deep Sleep power mode

  • Selectable voltage reference:

    • VDDA

    • Internal analog reference buffered through Opamp1 of CTB

    • External reference buffered through Opamp1 of CTB

  • Selectable output paths:

    • Direct DAC output to a pin

    • Buffered DAC output through Opamp0 of CTB

    • Sample and hold output path through Opamp0 of CTB

  • Selectable input modes:

    • Unsigned 12-bit mode

    • Virtual signed 12-bit mode

  • Configurable update rate using clock or strobe signal

  • Double buffered DAC voltage control register

  • Interrupt and DMA trigger on DAC buffer empty

  • Configurable as PGA along with Opamp1 of the CTB

The CTDAC generates a 12-bit DAC output voltage from the reference. The DAC reference can come from VDDA or from any signal buffered through Opamp0 of the CTB. This can be an external signal through a GPIO or from the internal AREF. The CTDAC is closely integrated with the CTB block, which provides easy buffering of the DAC output voltage, buffered input reference voltage, and sample and hold for the DAC output. The CTDAC control interface provides control of the DAC output through CPU or DMA. This includes a double-buffered DAC voltage control register, clock input for programmable update rate, interrupt on DAC buffer empty, and trigger to DMA.


The CTDAC has two switches, CO6 for configuring the output path and CVD for the reference source.



Configure the CTDAC hardware block by calling Cy_CTDAC_Init. The base address of the CTDAC hardware can be found in the device-specific header file. If the buffers in the CTB are used for the reference source or the output, initialize the CTB hardware block. After both blocks are initialized, enable the CTB block before enabling the CTDAC block.

The driver also provides a Cy_CTDAC_FastInit function for fast and easy initialization of the CTDAC. The driver has pre-defined configuration structures for the four combinations of the reference and output buffers.

After initialization, call Cy_CTDAC_Enable to enable the hardware.

Update Modes

The CTDAC contains two registers:


    For direct firmware writes to update the current DAC value immediately. This register is written with Cy_CTDAC_SetValue.


    For buffered writes to update the DAC value at a periodic rate or with a strobe trigger input. This register is written with Cy_CTDAC_SetValueBuffered.

The update mode is selected during initialization with the cy_stc_ctdac_config_t::updateMode. Four of these modes require a dedicated clock resource and the driver can configure the clock during initialization (see cy_stc_ctdac_config_t).

Three of these modes use a strobe signal through the digital signal interface (DSI). This allows control of the buffered update timing from an external source, for example, by another chip peripheral or from an off-chip source.

Direct write

In this mode, the user writes directly into the CTDAC_VAL register using Cy_CTDAC_SetValue. The action of writing to this register will update the DAC output. This mode does not generate an interrupt or trigger signal. In this mode, a clock must not be configured. Additionally, calling Cy_CTDAC_SetValueBuffered does not update the DAC output.


Buffered write

In this mode, the user writes to the CTDAC_VAL_NXT register using Cy_CTDAC_SetValueBuffered. The rising edge of the clock will update the DAC output and generate the interrupt and trigger signals.

Whenever data is transferred from the CTDAC_VAL_NXT register, an interrupt is asserted the same time as the trigger. But while the trigger is automatically cleared after two PeriClk cycles, the user must clear the interrupt with Cy_CTDAC_ClearInterrupt.


Strobe edge sync

In this mode, the user writes to the CTDAC_VAL_NXT register using Cy_CTDAC_SetValueBuffered. Each rising edge of the DSI strobe input enables one subsequent update from the next rising edge of the clock. The DSI input must remain high for two PeriClk cycles and go low for another two PeriClk cycles to allow for the next update. This restricts the DSI strobe input frequency to the PeriClk frequency divided by four.


Strobe edge immediate

In this mode, the user writes to the CTDAC_VAL_NXT register using Cy_CTDAC_SetValueBuffered. The clock resource is used but set to a logic high. Therefore, each rising edge of the DSI strobe input immediately updates the DAC output.


Strobe level

In this mode, the user writes to the CTDAC_VAL_NXT register using Cy_CTDAC_SetValueBuffered. The DSI strobe input acts as a hardware enable signal. While the DSI strobe input is high, the mode behaves like the Buffered write mode. When the DSI strobe input is low, updates are disabled.


DAC Modes

The format of code stored in the CTDAC_VAL register can either be unsigned or signed two’s complemented. Only the first 12 bits of the register are used by the DAC so there is no need for sign extension. With the signed format, the DAC decodes the code in the register by adding 0x800. The DAC can output the register value or the register value plus 1 (see Cy_CTDAC_SetOutputMode).

12-bit unsigned code

12-bit two's complement signed code









0.5 * Vref

Vref * 2049 / 4096



Vref * 4095 / 4096


The expressions in the above table are based on an unbuffered DAC output. When the output is buffered, the input and output range of the buffer will affect the output voltage. See Opamp Input and Output Range in the CTB driver for more information.

Interrupts and Trigger

When data from the CTDAC_VAL_NXT is transferred to the CTDAC_VAL register, an interrupt and trigger output are generated. The trigger output can be used with a DMA block to update the CTDAC value register at high speeds without any CPU intervention. Alternatively, the interrupt output can be used when DMA is not available to update the CTDAC value register, but at a slower speed.

Recall with the Update Modes, the interrupt and trigger output are available in all modes except Direct write.

DMA Trigger

The CTDAC trigger output signal can be routed to a DMA block using the TrigMux (Trigger Multiplexer) to trigger an update to the CTDAC_VAL_NXT register. When making the required Cy_TrigMux_Connect calls, use the pre-defined enums, TRIG14_IN_PASS_TR_CTDAC_EMPTY and TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY.

Handling Interrupts

The following code snippet demonstrates how to implement a routine to handle the interrupt. The routine gets called when any CTDAC on the device generates an interrupt.

/* Scenario: An interrupt occurs when data is transferred from the CTDAC_VAL_NXT
 * register to the CTDAC_VAL register signaling that the CTDAC can accept a new value.
 * The ISR function should be used to update the CTDAC value. */

/* ISR function to handle the global CTDAC interrupt. */
void CTDAC_Interrupt(void)
    /* Clear the interrupt so that subsequent interrupts can be handled. */
    uint8_t intrStatus;
    /* Get the interrupt status for a specific CTDAC instance on the device. */
    intrStatus = Cy_CTDAC_GetInterruptStatus(CTDAC0);

    /* If the interrupt status is 1, the CTDAC is ready to accept a new value. */
    if (1UL == intrStatus)
        /* Set the next value to output. */
        Cy_CTDAC_SetValueBuffered(CTDAC0, nextValue);
The following code snippet demonstrates how to configure and enable the interrupt.

    /* Scenario: Configure and enable the global CTDAC interrupt. */
    const cy_stc_sysint_t DAC_IRQ_cfg = {
        #if (CY_CPU_CORTEX_M0P)
            /* .intrSrc         = */ NvicMux8_IRQn,             /* CM0+ interrupt is NVIC #8 */
            /* .cm0pSrc         = */ pass_interrupt_dacs_IRQn,  /* Source of NVIC #8 is the global CTDAC interrupt */
            /* .intrPriority    = */ 7UL                        /* Interrupt priority is 7 */
            /* .intrSrc         = */ pass_interrupt_dacs_IRQn,  /* Interrupt source is the global CTDAC interrupt */
            /* .intrPriority    = */ 7UL                        /* Interrupt priority is 7 */

    /* Configure the interrupt with vector at CTDAC_Interrupt() */
    (void)Cy_SysInt_Init(&DAC_IRQ_cfg, CTDAC_Interrupt);
    /* Enable the interrupt */
    /* Scenario: The DMA0 block is used to transfer data from a lookup table
     * to the DAC value register. This allows for high-speed data transfers without any CPU intervention. 
     * For this to work, the CTDAC trigger output must be routed to the DMA0 trigger input using trigger muxes. */

    /* Route the CTDAC trigger output to the trigger input of DMA0. */


The hardware has the ability to deglitch the output value every time it is updated. This prevents small glitches in the DAC output during an update to propagate to the pin or opamp input. When deglitch is enabled, a switch on the output path is forced open for a configurable number of PeriClk cycles. This deglitch time is calculated as:


The optimal and recommended deglitch time is 700 ns. Call Cy_CTDAC_SetDeglitchCycles to set DEGLITCH_CNT.

There are two switches used for deglitching.

  • Switch COS in the CTB between the DAC output and the Opamp0 input

  • Switch CO6 in the CTDAC between the DAC output and external pin

Call Cy_CTDAC_SetDeglitchMode to set the deglitch path. Match this with the output buffer selection. If the output is buffered through the CTB, select CY_CTDAC_DEGLITCHMODE_BUFFERED. If the output is unbuffered to a direct pin, select CY_CTDAC_DEGLITCHMODE_UNBUFFERED.


If deglitching is enabled, the hardware does not force the deglitch switches into a closed state during Deep Sleep mode. Therefore, there is a chance that the device enters Deep Sleep mode while the hardware is deglitching and the switches on the output path remain open. To ensure the DAC will operate properly in Deep Sleep when enabled, make sure to register the Cy_CTDAC_DeepSleepCallback before entering Deep Sleep mode.

Sample and Hold

When buffering the DAC output, the CTB has a Sample and Hold (SH) feature that can be used for saving power. The DAC output voltage is retained on an internal capacitor for a duration of time while the DAC output can be turned off. The DAC hardware needs to be turned on in a periodic fashion to recharge the hold capacitor. This feature is firmware controlled using a sequence of function calls. See Cy_CTB_DACSampleAndHold in the CTB driver.

The hold time depends on the supply and reference voltages. The following hold times are based on the time it takes for the buffered output to change by 1 LSB.

  • Hold time = 750 us @ Vref = VDDA , VDDA = 1.7 V

  • Hold time = 525 us @ Vref = VDDA , VDDA = 3.6 V

  • Hold time = 200 us @ Vref = 1.2 V, VDDA = 3.6 V

Low Power Support

The CTDAC driver provides a callback function to handle power mode transitions. If the CTDAC is configured for Deep Sleep operation and deglitching is enabled, the callback Cy_CTDAC_DeepSleepCallback must be registered before calling Cy_SysPm_CpuEnterDeepSleep. Refer to SysPm (System Power Management) driver for more information about power mode transitions and callback registration.

More Information

Refer to the technical reference manual (TRM) and the device datasheet.




Reason for Change


Minor documentation updates.

Documented MISRA 2012 violations. Updated Cy_CTDAC_ConfigureClock() function parameters description.


Minor documentation updates.

Documentation enhancement.


Flattened the organization of the driver source code into the single source directory and the single include directory.

Driver library directory-structure simplification.

Added register access layer. Use register access macros instead of direct register access using dereferenced pointers.

Makes register access device-independent, so that the PDL does not need to be recompiled for each supported part number.


Added low power support section. Minor documentation edits.

Documentation update and clarification


Initial version