Interrupt Masks

group group_dmac_macros_interrupt_masks

Defines

CY_DMAC_INTR_COMPLETION

Bit 0: Completion of data transfer(s) as specified by the descriptor’s interruptType setting.

CY_DMAC_INTR_SRC_BUS_ERROR

Bit 1: Bus error for a load from the source.

CY_DMAC_INTR_DST_BUS_ERROR

Bit 2: Bus error for a store to the destination.

CY_DMAC_INTR_SRC_MISAL

Bit 3: Misalignment of the source address.

CY_DMAC_INTR_DST_MISAL

Bit 4: Misalignment of the destination address.

CY_DMAC_INTR_CURR_PTR_NULL

Bit 5: The channel is enabled and the current descriptor pointer is “0”.

CY_DMAC_INTR_ACTIVE_CH_DISABLED

Bit 6: The channel is disabled and the data transfer engine is busy.

CY_DMAC_INTR_DESCR_BUS_ERROR

Bit 7: Bus error for a load of the descriptor.