GPIO (General Purpose Input Output)

group group_gpio

The GPIO driver provides an API to configure and access device Input/Output pins.

The functions and other declarations used in this driver are in cy_gpio.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.

IO pins include all general purpose types such as GPIO, SIO, HSIO, AUXIO, and their variants.

Initialization can be performed either at the port level or by configuring the individual pins. For efficient use of code space, port configuration should be used in the field. Refer to the product device header files for the list of supported ports and pins.

A port is represented by GPIO_PRT_Type and a pin is represented by a number 0 to 7.

For PSoC 64 devices the the un-intended protected pins (due to constrain on PPU configuration) are modified using PRA driver. But the GPIO diver does not modify the intended protected pins .

Once the pin/port initialization is complete, each pin can be accessed by specifying the port (GPIO_PRT_Type) and the pin (0-7) in the provided API functions.

Configuration Considerations

  1. Pin multiplexing is controlled through the High-Speed IO Matrix (HSIOM) selection. This allows the pin to connect to signal sources/sinks throughout the device, as defined by the pin HSIOM selection options (en_hsiom_sel_t).

  2. All pins are initialized to High-Z drive mode with HSIOM connected to CPU (SW control digital pin only) at Power-On-Reset(POR).

  3. Some API functions perform read-modify-write operations on shared port registers. These functions are not thread safe and care must be taken when called by the application.

  4. Digital input buffer provides a high-impedance buffer for the external digital input. The input buffer is connected to the HSIOM for routing to the CPU port registers and selected peripheral. Enabling the input buffer provides possibility to read the pin state via the CPU. If pin is connected to an analog signal, the input buffer should be disabled to avoid crowbar currents. For more information refer to device TRM and the device datasheet.

Multiple pins on a port can be updated using direct port register writes with an appropriate port mask. An example is shown below, highlighting the different ways of configuring Port 1 pins using:

  • Initialize a Pin using cy_stc_gpio_pin_config_t structure

    
        cy_stc_gpio_pin_config_t pinConfig = {
            /*.outVal =*/ 1UL,                  /* Output = High */
            /*.driveMode =*/ CY_GPIO_DM_PULLUP, /* Resistive pull-up, input buffer on */
            /*.hsiom =*/ P0_3_GPIO,             /* Software controlled pin */
            /*.intEdge =*/ CY_GPIO_INTR_RISING, /* Rising edge interrupt */
            /*.intMask =*/ 1UL,                 /* Enable port interrupt for this pin */
            /*.vtrip =*/ CY_GPIO_VTRIP_CMOS,    /* CMOS voltage trip */
            /*.slewRate =*/ CY_GPIO_SLEW_FAST,  /* Fast slew rate */
            /*.driveSel =*/ CY_GPIO_DRIVE_FULL, /* Full drive strength */
            /*.vregEn =*/ 0UL,                  /* SIO-specific setting - ignored */
            /*.ibufMode =*/ 0UL,                /* SIO-specific setting - ignored */
            /*.vtripSel =*/ 0UL,                /* SIO-specific setting - ignored */
            /*.vrefSel =*/ 0UL,                 /* SIO-specific setting - ignored */
            /*.vohSel =*/ 0UL                   /* SIO-specific setting - ignored */
        };
        
        /* Initialize pin P0.3 */
        if(CY_GPIO_SUCCESS != Cy_GPIO_Pin_Init(P0_3_PORT, P0_3_NUM, &pinConfig))
        {
            /* Insert error handling */
        }
    

  • Initialize entire port using cy_stc_gpio_prt_config_t structure

        /* Scenario: Initialize GPIO port 0:
         * - 3 pin as input with resistive pull-up and rising edge interrupt;
         * - 5 pin as output in a strong drive mode with initial state high. */
        #define PIN_INPUT_NUM   3u
        #define PIN_OUTPUT_NUM  5u
        
        #define PIN_HIGH        1u
        #define INTR_ENABLE     1u
        #define INTR_CFG_LEN    2u
        #define PIN_DM_CFG_LEN  4u
        
        cy_stc_gpio_prt_config_t portConfig = {
            /*.out        =*/ (PIN_HIGH << PIN_OUTPUT_NUM),                                 /* PX.5 output value = 1 */
            /*.intrMask   =*/ (INTR_ENABLE << PIN_INPUT_NUM),                               /* PX.3 interrupt enabled */
            /*.intrCfg    =*/ (CY_GPIO_INTR_RISING << (PIN_INPUT_NUM * INTR_CFG_LEN)),      /* PX.3 rising edge interrupt */
            /*.cfg        =*/ ((CY_GPIO_DM_PULLUP << (PIN_INPUT_NUM  * PIN_DM_CFG_LEN)) |   /* PX.3 resistive pull-up */
                              (CY_GPIO_DM_STRONG << (PIN_OUTPUT_NUM  * PIN_DM_CFG_LEN))),   /* PX.5 strong drive */
            /*.cfgIn      =*/ 0x00000000u,                                                  /* PX[7:0] CMOS trip (default value)*/
            /*.cfgOut     =*/ 0x00000000u,                                                  /* PX[7:0] Fast slew rate, full drive strength (default value) */
            /*.cfgSIO     =*/ 0x00000000u,                                                  /* PX[7:0] ignored (default value) */
            /*.sel0Active =*/ 0x00000000u,                                                  /* PX[3:0] Use GPIO HSIOM (default value) */
            /*.sel1Active =*/ 0x00000000u,                                                  /* PX[7:4] Use GPIO HSIOM (default value) */
        };
    
        /* Initialize GPIO port 0 */
        if(CY_GPIO_SUCCESS != Cy_GPIO_Port_Init(GPIO_PRT0, &portConfig))
        {
            /* Insert error handling */
        }
        
    

  • Port output data register

  • Port output data set register

  • Port output data clear register

    GPIO_PRT_Type* portAddr;
    uint8_t value;
    
    /* Set the port address */
    portAddr = GPIO_PRT1;
    
    /* Set the drive mode to STRONG for pins P1[0], P1[2] and P1[3] (other pins in this port are HIGHZ) */
    CY_SET_REG32(&portAddr->CFG, CY_GPIO_DM_STRONG_IN_OFF << GPIO_PRT_CFG_DRIVE_MODE0_Pos | 
                                 CY_GPIO_DM_STRONG_IN_OFF << GPIO_PRT_CFG_DRIVE_MODE2_Pos | 
                                 CY_GPIO_DM_STRONG_IN_OFF << GPIO_PRT_CFG_DRIVE_MODE3_Pos );
    
    /* Set the pins P1[0], P1[2] and P1[3] to high and other pins in this port to low */
    CY_SET_REG32(&portAddr->OUT, GPIO_PRT_OUT_OUT0_Msk | 
                                 GPIO_PRT_OUT_OUT2_Msk | 
                                 GPIO_PRT_OUT_OUT3_Msk);
    
    /* Set the pins P1[2] and P1[3] to low (other pins in this port are unchanged) */
    CY_SET_REG32(&portAddr->OUT_CLR, GPIO_PRT_OUT_CLR_OUT2_Msk | 
                                     GPIO_PRT_OUT_CLR_OUT3_Msk);
    
    /* Set the pin P1[3] to high again (other pins in this port are unchanged) */
    CY_SET_REG32(&portAddr->OUT_SET, GPIO_PRT_OUT_SET_OUT3_Msk);
    
    /* Read the port data (value should be 0b00001001) */
    value = CY_GET_REG32(&portAddr->OUT);

    /* Set pin P1[3] to low (other pins are not impacted) */
    CY_SET_REG32(&portAddr->OUT, _CLR_SET_FLD32U(portAddr->OUT, GPIO_PRT_OUT_OUT3, 0u));
     
    /* Set pin P1[2] to high (other pins are not impacted) */
    CY_SET_REG32(&portAddr->OUT, _CLR_SET_FLD32U(portAddr->OUT, GPIO_PRT_OUT_OUT2, 1u));

More Information

Refer to the technical reference manual (TRM) and the device datasheet.

Changelog

Version

Changes

Reason for Change

1.50

Modified Cy_GPIO_Pin_Init, Cy_GPIO_Pin_FastInit, and Cy_GPIO_SetDrivemode APIs to catch wrong drive modes.

Defect fix.

1.40

Changes in Support of the new family of devices

Added new family of devices

Changes in support of Secure pins used for External clocks on Secure devices

Added support for accessing External clocks protected pins

1.30

Fixed/documented MISRA 2012 violations.

MISRA 2012 compliance.

1.20.1

Minor documentation updates.

Documentation enhancement.

1.20

Flattened the organization of the driver source code into the single source directory and the single include directory.

Driver library directory-structure simplification.

Added the functions for configuring the AMux bus splitter switch cells:

Added a new functionality related to AMux bus.

Added register access layer. Use register access macros instead of direct register access using dereferenced pointers.

Makes register access device-independent, so that the PDL does not need to be recompiled for each supported part number.

1.10.1

Updated description for the functions: Cy_GPIO_GetInterruptStatus, Cy_GPIO_GetInterruptMask, Cy_GPIO_GetInterruptStatusMasked.

Minor documentation edits.

Documentation update and clarification

1.10

Added input parameter validation to the API functions

1.0

Initial version