GPIO Functions

group group_gpio_functions_gpio

Functions

void Cy_GPIO_SetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxconnect_t amuxConnect, cy_en_gpio_amuxselect_t amuxBus)

Configure a specific AMux bus splitter switch cell into a specific configuration.

note

This API is available for the CAT1A devices.

Parameters
  • switchCtrl: Selects specific AMux bus splitter cell between two segments. The cy_en_amux_split_t enumeration can be found in the GPIO header file for the device package.

  • amuxConnect: Selects configuration of the three switches within the splitter cell

  • amuxBus: Selects which AMux bus within the splitter is being configured

cy_en_gpio_amuxconnect_t Cy_GPIO_GetAmuxSplit(cy_en_amux_split_t switchCtrl, cy_en_gpio_amuxselect_t amuxBus)

Returns the configuration of a specific AMux bus splitter switch cell.

note

This API is available for the CAT1A devices.

Return

Returns configuration of the three switches in the selected splitter cell

Parameters
  • switchCtrl: Selects specific AMux bus splitter cell between two segments. The cy_en_amux_split_t enumeration can be found in the GPIO header file for the device package.

  • amuxBus: Selects which AMux bus within the splitter is being configured

uint32_t Cy_GPIO_Read(GPIO_PRT_Type *base, uint32_t pinNum)

Reads the current logic level on the input buffer of the pin.

Return

Logic level present on the pin

Function Usage


    /* Scenario: P0.3 was initialized and input buffer enabled */
    
    /* Read the input state of P0.3 */
    if(1UL == Cy_GPIO_Read(P0_3_PORT, P0_3_NUM))
    {
        /* Insert logic for High pin state */
    }
    else
    {
        /* Insert logic for Low pin state */
    }

Parameters
  • base: Pointer to the pin’s port register base address

  • pinNum: Position of the pin bit-field within the port register. Bit position 8 is the routed pin through the port glitch filter.

void Cy_GPIO_Write(GPIO_PRT_Type *base, uint32_t pinNum, uint32_t value)

Write a logic 0 or logic 1 state to the output driver.

This function should be used only for software driven pins. It does not have any effect on peripheral driven pins.

Function Usage


    uint32_t pinState = 0UL;
    
    /* Control P0.3 based on the pinState variable */
    Cy_GPIO_Write(P0_3_PORT, P0_3_NUM, pinState);

Parameters
  • base: Pointer to the pin’s port register base address

  • pinNum: Position of the pin bit-field within the port register

  • value: Logic level to drive out on the pin

uint32_t Cy_GPIO_ReadOut(GPIO_PRT_Type *base, uint32_t pinNum)

Reads the current logic level on the pin output driver.

Return

Logic level on the pin output driver

Function Usage


    /* Write logic low to P0.3 */
    Cy_GPIO_Write(P0_3_PORT, P0_3_NUM, 0UL);
    
    /* Get the output value of P0.3 */
    if(0UL != Cy_GPIO_ReadOut(P0_3_PORT, P0_3_NUM))
    {
        /* Insert error handling */
    }

Parameters
  • base: Pointer to the pin’s port register base address

  • pinNum: Position of the pin bit-field within the port register

void Cy_GPIO_Set(GPIO_PRT_Type *base, uint32_t pinNum)

Set a pin output to logic state high.

This function should be used only for software driven pins. It does not have any effect on peripheral driven pins.

Function Usage


    /* Set P0.3 (out value = High) */
    Cy_GPIO_Set(P0_3_PORT, P0_3_NUM);

Parameters
  • base: Pointer to the pin’s port register base address

  • pinNum: Position of the pin bit-field within the port register

void Cy_GPIO_Clr(GPIO_PRT_Type *base, uint32_t pinNum)

Set a pin output to logic state Low.

This function should be used only for software driven pins. It does not have any effect on peripheral driven pins.

Function Usage


    /* Clear P0.3 (out value = Low) */
    Cy_GPIO_Clr(P0_3_PORT, P0_3_NUM);

Parameters
  • base: Pointer to the pin’s port register base address

  • pinNum: Position of the pin bit-field within the port register

void Cy_GPIO_Inv(GPIO_PRT_Type *base, uint32_t pinNum)

Set a pin output logic state to the inverse of the current output logic state.

This function should be used only for software driven pins. It does not have any effect on peripheral driven pins.

Function Usage


    /* Invert P0.3 (out value = ~(out value)) */
    Cy_GPIO_Inv(P0_3_PORT, P0_3_NUM);

Parameters
  • base: Pointer to the pin’s port register base address

  • pinNum: Position of the pin bit-field within the port register

void Cy_GPIO_SetDrivemode(GPIO_PRT_Type *base, uint32_t pinNum, uint32_t value)

Configures the pin output buffer drive mode and input buffer enable.

The output buffer drive mode and input buffer enable are combined into a single parameter. The drive mode controls the behavior of the pin in general. Enabling the input buffer allows the digital pin state to be read but also contributes to extra current consumption.

note

This function modifies a port register in a read-modify-write operation. It is not thread safe as the resource is shared among multiple pins on a port.

Function Usage


    /* Scenario: Enter deep-sleep with reduced leakage current on P0.3 */
    
    /* Get the drive mode of P0.3 */
    if(CY_GPIO_DM_STRONG== Cy_GPIO_GetDrivemode(P0_3_PORT, P0_3_NUM))
    {
        /* Change the drive mode of P0.3 to analog (hi-z, input buffer off) */
        Cy_GPIO_SetDrivemode(P0_3_PORT, P0_3_NUM, CY_GPIO_DM_ANALOG);
    }

Parameters
  • base: Pointer to the pin’s port register base address

  • pinNum: Position of the pin bit-field within the port register

  • value: Pin drive mode. Options are detailed in Pin drive mode macros

uint32_t Cy_GPIO_GetDrivemode(GPIO_PRT_Type *base, uint32_t pinNum)

Returns the pin output buffer drive mode and input buffer enable state.

Return

Pin drive mode. Options are detailed in Pin drive mode macros

Function Usage


    /* Scenario: Enter deep-sleep with reduced leakage current on P0.3 */
    
    /* Get the drive mode of P0.3 */
    if(CY_GPIO_DM_STRONG== Cy_GPIO_GetDrivemode(P0_3_PORT, P0_3_NUM))
    {
        /* Change the drive mode of P0.3 to analog (hi-z, input buffer off) */
        Cy_GPIO_SetDrivemode(P0_3_PORT, P0_3_NUM, CY_GPIO_DM_ANALOG);
    }

Parameters
  • base: Pointer to the pin’s port register base address

  • pinNum: Position of the pin bit-field within the port register

void Cy_GPIO_SetVtrip(GPIO_PRT_Type *base, uint32_t pinNum, uint32_t value)

Configures the GPIO pin input buffer voltage threshold mode.

note

This function modifies a port register in a read-modify-write operation. It is not thread safe as the resource is shared among multiple pins on a port.

Function Usage


    /* Scenario: Connect the pin to a TTL hardware */
    
    /* Get the vtrip value of P0.3 */
    if(CY_GPIO_VTRIP_CMOS == Cy_GPIO_GetVtrip(P0_3_PORT, P0_3_NUM))
    {
        /* Change the vtrip of P0.3 to LVTTL */
        Cy_GPIO_SetVtrip(P0_3_PORT, P0_3_NUM, CY_GPIO_VTRIP_TTL);
    }

Parameters
  • base: Pointer to the pin’s port register base address

  • pinNum: Position of the pin bit-field within the port register

  • value: Pin voltage threshold mode. Options are detailed in Voltage trip mode macros

uint32_t Cy_GPIO_GetVtrip(GPIO_PRT_Type *base, uint32_t pinNum)

Returns the pin input buffer voltage threshold mode.

Return

Pin voltage threshold mode. Options are detailed in Voltage trip mode macros

Function Usage


    /* Scenario: Connect the pin to a TTL hardware */
    
    /* Get the vtrip value of P0.3 */
    if(CY_GPIO_VTRIP_CMOS == Cy_GPIO_GetVtrip(P0_3_PORT, P0_3_NUM))
    {
        /* Change the vtrip of P0.3 to LVTTL */
        Cy_GPIO_SetVtrip(P0_3_PORT, P0_3_NUM, CY_GPIO_VTRIP_TTL);
    }

Parameters
  • base: Pointer to the pin’s port register base address

  • pinNum: Position of the pin bit-field within the port register

void Cy_GPIO_SetSlewRate(GPIO_PRT_Type *base, uint32_t pinNum, uint32_t value)

Configures the pin output buffer slew rate.

GPIO pins have fast and slow output slew rate options for the strong drivers configured using this API. By default the port works in fast slew mode. Slower slew rate results in reduced EMI and crosstalk and are recommended for low-frequency signals or signals without strict timing constraints.

note

This function has no effect for the GPIO ports, where the slew rate configuration is not available. Refer to device datasheet for details.

note

This function modifies a port register in a read-modify-write operation. It is not thread safe as the resource is shared among multiple pins on a port.

Function Usage


    /* Scenario: Connect the pin to I2C (slow slew rate is preferred for low EMI) */
    
    /* Get the slew rate value of P0.3 */
    if(CY_GPIO_SLEW_FAST == Cy_GPIO_GetSlewRate(P0_3_PORT, P0_3_NUM))
    {
        /* Change the slew rate of P0.3 to Slow */
        Cy_GPIO_SetSlewRate(P0_3_PORT, P0_3_NUM, CY_GPIO_SLEW_SLOW);
    }

Parameters
  • base: Pointer to the pin’s port register base address

  • pinNum: Position of the pin bit-field within the port register

  • value: Pin slew rate. Options are detailed in Slew Rate Mode macros

uint32_t Cy_GPIO_GetSlewRate(GPIO_PRT_Type *base, uint32_t pinNum)

Returns the pin output buffer slew rate.

Return

Pin slew rate. Options are detailed in Slew Rate Mode macros

Function Usage


    /* Scenario: Connect the pin to I2C (slow slew rate is preferred for low EMI) */
    
    /* Get the slew rate value of P0.3 */
    if(CY_GPIO_SLEW_FAST == Cy_GPIO_GetSlewRate(P0_3_PORT, P0_3_NUM))
    {
        /* Change the slew rate of P0.3 to Slow */
        Cy_GPIO_SetSlewRate(P0_3_PORT, P0_3_NUM, CY_GPIO_SLEW_SLOW);
    }

Parameters
  • base: Pointer to the pin’s port register base address

  • pinNum: Position of the pin bit-field within the port register

void Cy_GPIO_SetDriveSel(GPIO_PRT_Type *base, uint32_t pinNum, uint32_t value)

Configures the pin output buffer drive strength.

The drive strength field determines the active portion of the output drivers used and can affect the slew rate of output signals. Drive strength options are full drive strength (default), one-half strength, one-quarter strength, and oneeighth strength. Drive strength must be set to full drive strength when the slow slew rate bit (SLOW) is set.

note

This function modifies a port register in a read-modify-write operation. It is not thread safe as the resource is shared among multiple pins on a port.

Function Usage


    /* Scenario: Reduce the drive current as part of power conservation strategy */
    
    /* Get the drive current capability of P0.3 */
    if(CY_GPIO_DRIVE_FULL == Cy_GPIO_GetDriveSel(P0_3_PORT, P0_3_NUM))
    {
        /* Change the drive current capability of P0.3 to 1/4 of full strength */
        Cy_GPIO_SetDriveSel(P0_3_PORT, P0_3_NUM, CY_GPIO_DRIVE_1_4);
    }

Parameters
  • base: Pointer to the pin’s port register base address

  • pinNum: Position of the pin bit-field within the port register.

  • value: Pin drive strength. Options are detailed in Pin drive strength macros

uint32_t Cy_GPIO_GetDriveSel(GPIO_PRT_Type *base, uint32_t pinNum)

Returns the pin output buffer drive strength.

Return

Pin drive strength. Options are detailed in Pin drive strength macros

Function Usage


    /* Scenario: Reduce the drive current as part of power conservation strategy */
    
    /* Get the drive current capability of P0.3 */
    if(CY_GPIO_DRIVE_FULL == Cy_GPIO_GetDriveSel(P0_3_PORT, P0_3_NUM))
    {
        /* Change the drive current capability of P0.3 to 1/4 of full strength */
        Cy_GPIO_SetDriveSel(P0_3_PORT, P0_3_NUM, CY_GPIO_DRIVE_1_4);
    }

Parameters
  • base: Pointer to the pin’s port register base address

  • pinNum: Position of the pin bit-field within the port register