Interrupt Masks

group group_i2s_macros_interrupt_masks

Defines

CY_I2S_INTR_TX_TRIGGER

Bit 0: Less entries in the TX FIFO than specified by Trigger Level.

CY_I2S_INTR_TX_NOT_FULL

Bit 1: TX FIFO is not full.

CY_I2S_INTR_TX_EMPTY

Bit 4: TX FIFO is empty, i.e.

it has 0 entries.

CY_I2S_INTR_TX_OVERFLOW

Bit 5: Attempt to write to a full TX FIFO.

CY_I2S_INTR_TX_UNDERFLOW

Bit 6: Attempt to read from an empty TX FIFO.

This happens when the IP is ready to transfer data and TX_EMPTY is ‘1’.

CY_I2S_INTR_TX_WD

Bit 8: Tx watchdog event occurs.

CY_I2S_INTR_RX_TRIGGER

Bit 16: More entries in the RX FIFO than specified by Trigger Level.

CY_I2S_INTR_RX_NOT_EMPTY

Bit 18: RX FIFO is not empty.

CY_I2S_INTR_RX_FULL

Bit 19: RX FIFO is full.

CY_I2S_INTR_RX_OVERFLOW

Bit 21: Attempt to write to a full RX FIFO.

CY_I2S_INTR_RX_UNDERFLOW

Bit 22: Attempt to read from an empty RX FIFO.

CY_I2S_INTR_RX_WD

Bit 24: Rx watchdog event occurs.