Data Structures¶
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group
group_pra_stc
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struct
cy_stc_pra_system_config_t
- #include <cy_pra_cfg.h>
System configuration structure.
Public Members
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bool
powerEnable
Power is enabled or disabled.
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bool
ldoEnable
Core Regulator.
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bool
pmicEnable
Power using external PMIC output.
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bool
vBackupVDDDEnable
vBackup source using VDD or Direct supply
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bool
ulpEnable
System Active Power mode is ULP.
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bool
ecoEnable
ECO Enable.
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bool
extClkEnable
EXTCLK Enable.
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bool
iloEnable
ILO Enable.
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bool
wcoEnable
WCO Enable.
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bool
fllEnable
FLL Enable.
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bool
pll0Enable
PLL0 Enable.
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bool
pll1Enable
PLL1 Enable.
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bool
path0Enable
PATH_MUX0 Enable.
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bool
path1Enable
PATH_MUX1 Enable.
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bool
path2Enable
PATH_MUX2 Enable.
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bool
path3Enable
PATH_MUX3 Enable.
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bool
path4Enable
PATH_MUX4 Enable.
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bool
path5Enable
PATH_MUX5 Enable.
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bool
clkFastEnable
CLKFAST Enable.
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bool
clkPeriEnable
CLKPERI Enable.
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bool
clkSlowEnable
CLKSLOW Enable.
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bool
clkHF0Enable
CLKHF0 Enable.
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bool
clkHF1Enable
CLKHF1 Enable.
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bool
clkHF2Enable
CLKHF2 Enable.
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bool
clkHF3Enable
CLKHF3 Enable.
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bool
clkHF4Enable
CLKHF4 Enable.
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bool
clkHF5Enable
CLKHF5 Enable.
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bool
clkPumpEnable
CLKPUMP Enable.
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bool
clkLFEnable
CLKLF Enable.
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bool
clkBakEnable
CLKBAK Enable.
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bool
clkTimerEnable
CLKTIMER Enable.
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bool
clkAltSysTickEnable
CLKALTSYSTICK Enable.
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bool
piloEnable
PILO Enable.
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bool
clkAltHfEnable
BLE ECO Clock Enable.
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cy_en_syspm_ldo_voltage_t
ldoVoltage
LDO Voltage (LP or ULP)
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cy_en_syspm_buck_voltage1_t
buckVoltage
Buck Voltage.
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bool
pwrCurrentModeMin
Minimum core regulator current mode.
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uint32_t
ecoFreqHz
ECO Frequency in Hz.
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uint32_t
ecoLoad
Parallel Load Capacitance (pF)
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uint32_t
ecoEsr
Equivalent series resistance (ohm)
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uint32_t
ecoDriveLevel
Drive Level (uW)
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GPIO_PRT_Type *
ecoInPort
ECO input port.
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GPIO_PRT_Type *
ecoOutPort
ECO output port.
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uint32_t
ecoInPinNum
ECO input pin number.
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uint32_t
ecoOutPinNum
ECO output pin number.
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uint32_t
extClkFreqHz
External clock frequency in Hz.
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GPIO_PRT_Type *
extClkPort
External connection port.
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uint32_t
extClkPinNum
External connection pin.
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en_hsiom_sel_t
extClkHsiom
IO mux value.
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bool
iloHibernateON
Run in Hibernate Mode.
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bool
bypassEnable
Clock port bypass to External sine wave or to normal crystal.
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GPIO_PRT_Type *
wcoInPort
WCO Input port.
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GPIO_PRT_Type *
wcoOutPort
WCO Output port.
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uint32_t
wcoInPinNum
WCO Input pin.
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uint32_t
wcoOutPinNum
WCO Output pin.
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uint32_t
fllOutFreqHz
FLL Output Frequency in Hz.
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uint32_t
fllMult
CLK_FLL_CONFIG register, FLL_MULT bits.
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uint16_t
fllRefDiv
CLK_FLL_CONFIG2 register, FLL_REF_DIV bits.
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cy_en_fll_cco_ranges_t
fllCcoRange
CLK_FLL_CONFIG4 register, CCO_RANGE bits.
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bool
enableOutputDiv
CLK_FLL_CONFIG register, FLL_OUTPUT_DIV bit.
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uint16_t
lockTolerance
CLK_FLL_CONFIG2 register, LOCK_TOL bits.
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uint8_t
igain
CLK_FLL_CONFIG3 register, FLL_LF_IGAIN bits.
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uint8_t
pgain
CLK_FLL_CONFIG3 register, FLL_LF_PGAIN bits.
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uint16_t
settlingCount
CLK_FLL_CONFIG3 register, SETTLING_COUNT bits.
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cy_en_fll_pll_output_mode_t
outputMode
CLK_FLL_CONFIG3 register, BYPASS_SEL bits.
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uint16_t
ccoFreq
CLK_FLL_CONFIG4 register, CCO_FREQ bits.
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uint32_t
pll0OutFreqHz
PLL0 output frequency in Hz.
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uint8_t
pll0FeedbackDiv
PLL0 CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits.
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uint8_t
pll0ReferenceDiv
PLL0 CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits.
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uint8_t
pll0OutputDiv
PLL0 CLK_PLL_CONFIG register, OUTPUT_DIV bits.
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bool
pll0LfMode
PLL0 CLK_PLL_CONFIG register, PLL_LF_MODE bit.
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cy_en_fll_pll_output_mode_t
pll0OutputMode
PLL0 CLK_PLL_CONFIG register, BYPASS_SEL bits.
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uint32_t
pll1OutFreqHz
PLL1 output frequency in Hz.
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uint8_t
pll1FeedbackDiv
PLL1 CLK_PLL_CONFIG register, FEEDBACK_DIV (P) bits.
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uint8_t
pll1ReferenceDiv
PLL1 CLK_PLL_CONFIG register, REFERENCE_DIV (Q) bits.
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uint8_t
pll1OutputDiv
PLL1 CLK_PLL_CONFIG register, OUTPUT_DIV bits.
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bool
pll1LfMode
PLL1 CLK_PLL_CONFIG register, PLL_LF_MODE bit.
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cy_en_fll_pll_output_mode_t
pll1OutputMode
PLL1 CLK_PLL_CONFIG register, BYPASS_SEL bits.
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cy_en_clkpath_in_sources_t
path0Src
Input multiplexer0 clock source.
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cy_en_clkpath_in_sources_t
path1Src
Input multiplexer1 clock source.
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cy_en_clkpath_in_sources_t
path2Src
Input multiplexer2 clock source.
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cy_en_clkpath_in_sources_t
path3Src
Input multiplexer3 clock source.
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cy_en_clkpath_in_sources_t
path4Src
Input multiplexer4 clock source.
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cy_en_clkpath_in_sources_t
path5Src
Input multiplexer5 clock source.
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uint8_t
clkFastDiv
Fast clock divider.
User has to pass actual divider-1
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uint8_t
clkPeriDiv
Peri clock divider.
User has to pass actual divider-1
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uint8_t
clkSlowDiv
Slow clock divider.
User has to pass actual divider-1
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cy_en_clkhf_in_sources_t
hf0Source
HF0 Source Clock Path.
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cy_en_clkhf_dividers_t
hf0Divider
HF0 Divider.
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uint32_t
hf0OutFreqMHz
HF0 Output Frequency in MHz.
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cy_en_clkhf_in_sources_t
hf1Source
HF1 Source Clock Path.
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cy_en_clkhf_dividers_t
hf1Divider
HF1 Divider.
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uint32_t
hf1OutFreqMHz
HF1 Output Frequency in MHz.
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cy_en_clkhf_in_sources_t
hf2Source
HF2 Source Clock Path.
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cy_en_clkhf_dividers_t
hf2Divider
HF2 Divider.
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uint32_t
hf2OutFreqMHz
HF2 Output Frequency in MHz.
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cy_en_clkhf_in_sources_t
hf3Source
HF3 Source Clock Path.
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cy_en_clkhf_dividers_t
hf3Divider
HF3 Divider.
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uint32_t
hf3OutFreqMHz
HF3 Output Frequency in MHz.
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cy_en_clkhf_in_sources_t
hf4Source
HF4 Source Clock Path.
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cy_en_clkhf_dividers_t
hf4Divider
HF4 Divider.
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uint32_t
hf4OutFreqMHz
HF4 Output Frequency in MHz.
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cy_en_clkhf_in_sources_t
hf5Source
HF5 Source Clock Path.
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cy_en_clkhf_dividers_t
hf5Divider
HF5 Divider.
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uint32_t
hf5OutFreqMHz
HF5 Output Frequency in MHz.
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cy_en_clkpump_in_sources_t
pumpSource
PUMP Source Clock Path.
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cy_en_clkpump_divide_t
pumpDivider
PUMP Divider.
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cy_en_clklf_in_sources_t
clkLfSource
Clock LF Source.
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cy_en_clkbak_in_sources_t
clkBakSource
Clock Backup domain Source.
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cy_en_clktimer_in_sources_t
clkTimerSource
Clock Timer Source.
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uint8_t
clkTimerDivider
Clock Timer Divider.
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cy_en_systick_clock_source_t
clkSrcAltSysTick
SysTick Source.
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uint32_t
altHFcLoad
Load Cap (pF)
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uint32_t
altHFxtalStartUpTime
Startup Time (us)
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uint32_t
altHFclkFreq
Clock Frequency.
0 -> 16MHz and 1 -> 32MHz. Any other value except 0 and 1 is invalid
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uint32_t
altHFsysClkDiv
Clock Divider.
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uint32_t
altHFvoltageReg
BLE Voltage Regulator.
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bool
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struct