SCB (Serial Communication Block)¶
The Serial Communications Block (SCB) supports three serial communication protocols: Serial Peripheral Interface (SPI), Universal Asynchronous Receiver Transmitter (UART), and Inter Integrated Circuit (I2C or IIC).
Only one of the protocols is supported by an SCB at any given time.
The functions and other declarations used in this driver are in cy_scb_spi.h, cy_scb_uart.h, cy_scb_ezi2c.h, cy_scb_i2c.h respectively. Include cy_pdl.h to get access to all functions and declarations in the PDL.
For more information on the SCB peripheral, refer to the technical reference manual (TRM).
Reason for Change
Newly added API's for runtime parameter set/get functionality which include Cy_SCB_UART_SetOverSample to set oversample bits of UART, Cy_SCB_UART_GetOverSample to add return value of oversample, Cy_SCB_UART_GetDataWidth to get data width, Cy_SCB_UART_SetDataWidth to set data width, Cy_SCB_UART_GetParity to get parity, Cy_SCB_UART_SetParity to set parity, Cy_SCB_UART_GetStopBits to get stop bits, Cy_SCB_UART_SetStopBits to set stop bits, Cy_SCB_UART_GetDropOnParityError to get drop on parity error, Cy_SCB_UART_SetDropOnParityError to set drop on parity error, Cy_SCB_UART_GetEnableMsbFirst to get enable MSB first and Cy_SCB_UART_SetEnableMsbFirst to set enable MSB first.
Runtime Parameter update.
Newly added API's which include Cy_SCB_Get_RxDataWidth to return the RX data width, Cy_SCB_Get_TxDataWidth to return the TX data width, Cy_SCB_SetMemWidth to set the RX and TX FIFOs byte mode/halfword/word mode. Updated Structures cy_stc_scb_uart_config_t, cy_en_scb_spi_parity_t, cy_stc_scb_spi_config_t.
New device support.
Fixed the Cy_SCB_UART_GetNumInRingBuffer function to return correct number of the elements in ring buffer.
Cy_SCB_UART_GetNumInRingBuffer function works incorrectly, when write pointer of the ring buffer is behind the read pointer.
Fixed/Documented MISRA 2012 violations.
MISRA 2012 compliance.
Fixed the Cy_SCB_SPI_SetActiveSlaveSelectPolarity function to properly configure the polarity of the slave select line.
Cy_SCB_SPI_SetActiveSlaveSelectPolarity function works incorrectly.
Minor documentation updates.
Update level selection logic of RX FIFO trigger in the Cy_SCB_UART_Receive().
Fix possible stuck if the RTS level is less than the RX FIFO level.
Exclude self-test assertion macros under release build profile.
Avoid dependency on CY_ASSERT macro implementation.
Added header guards CY_IP_MXSCB.
To enable the PDL compilation with wounded out IP blocks.
Fixed MISRA violation.
Changed values CY_SCB_SPI_CPHA0_CPOL1 and CY_SCB_SPI_CPHA1_CPOL0 in enum cy_en_scb_spi_sclk_mode_t.
The incorrect values in cy_en_scb_spi_sclk_mode_t caused incorrect initialization of the combination of phases and polarity: "CHPA = 0, CPOL = 1" and "CHPA = 1, CPOL = 0".
Added new CY_SCB_UART_RECEIVE_NOT_EMTPY and CY_SCB_UART_TRANSMIT_EMTPY callback events UART Callback Events.
Extended the driver callback events to support the MBED-OS.
Merged SCB changelogs for each mode into one changelog.
Merged SCB MISRA-C Compliance sections for each mode into one section.
To optimize the SCB MISRA-C Compliance sections.
Documentation of the MISRA rule violation.
Flattened the organization of the driver source code into the single source directory and the single include directory.
Driver library directory-structure simplification.
Added register access layer. Use register access macros instead of direct register access using dereferenced pointers.
Makes register access device-independent, so that the PDL does not need to be recompiled for each supported part number.
Added the enableDigitalFilter, highPhaseDutyCycle and lowPhaseDutyCycle fields to the cy_stc_scb_i2c_config_t configuration structure.
Added the I2C master data rate configuration using the configuration structure.
Fixed the Cy_SCB_I2C_SetDataRate function to properly configure data rates greater than 400 kbps in Master and Master-Slave modes.
Added verification that clk_scb is within the valid range for the desired data rate.
The analog filter was enabled for all data rates in Master and Master-Slave modes. This prevents reaching the maximum supported data rate of 1000 kbps which requires a digital filter.
Fixed the ReStart condition generation sequence for a write transaction in the Cy_SCB_I2C_MasterWrite function.
The driver can notify about a zero length write transaction completion before the address byte is sent if the Cy_SCB_I2C_MasterWrite function execution was interrupted between setting the restart generation command and writing the address byte into the TX FIFO.
Improved the interrupt configuration options for the I2C slave and master mode configurations.
Updated the ReStart condition generation sequence for a write transaction in the Cy_SCB_I2C_MasterSendReStart function.
Added parameters validation for public API.
Fixed functions which return interrupt status to return only defined set of interrupt statuses.
Added missing "cy_cb_" to the callback function type names.
Replaced variables that have limited range of values with enumerated types.
Added function Cy_SCB_UART_SendBreakBlocking for break condition generation.
The callbacks allowed entering device into low power mode when RX FIFO had data.
Fixed SPI callback notification when error event occurred.
The SPI callback passed incorrect event value if error event occurred.
Fixed the Cy_SCB_I2C_MasterSendReStart function to properly generate the ReStart condition when the previous transaction was a write.
The master interpreted the address byte written into the TX FIFO as a data byte and continued a write transaction. The ReStart condition was generated after the master completed transferring the data byte. The SCL line was stretched by the master waiting for the address byte to be written into the TX FIFO after the ReStart condition generation. The following timeout detection released the bus from the master control.
Fixed the slave operation after the address byte was NACKed by the firmware.
The observed slave operation failure depends on whether Level 2 assert is enabled or not. Enabled: the device stuck in the fault handler due to the assert assignment in the Cy_SCB_I2C_Interrupt. Disabled: the slave sets the transaction completion status and notifies on the transaction completion event after the address was NACKed. The failure is observed only when the slave is configured to accept an address in the RX FIFO.
- EZI2C (SCB)
- I2C (SCB)
- SPI (SCB)
- UART (SCB)