Data Structures

group group_scb_spi_data_structures

Typedefs

typedef void (*cy_cb_scb_spi_handle_events_t)(uint32_t event)

Provides the typedef for the callback function called in the Cy_SCB_SPI_Interrupt to notify the user about occurrences of SPI Callback Events.

struct cy_stc_scb_spi_config_t
#include <cy_scb_spi.h>

SPI configuration structure.

Public Members

cy_en_scb_spi_mode_t spiMode

Specifies the mode of operation.

cy_en_scb_spi_sub_mode_t subMode

Specifies the submode of SPI operation.

cy_en_scb_spi_sclk_mode_t sclkMode

Configures the SCLK operation for Motorola sub-mode, ignored for all other submodes.

cy_en_scb_spi_parity_t parity

Configures the SPI parity.

note

This parameter is available for CAT1B devices.

bool dropOnParityError

Enables the hardware to drop data in the RX FIFO when a parity error is detected.

note

This parameter is available for CAT1B devices.

uint32_t oversample

Oversample factor for SPI.

  • For the master mode, the data rate is the SCB clock / oversample (the valid range is 4 to 16, when MISO is used; if MISO is not used then the valid range is 2 to 16).

  • For the slave mode, the oversample value is ignored. The data rate is determined by the SCB clock frequency.

uint32_t rxDataWidth

The width of RX data (valid range 4-16).

It must be the same as txDataWidth except in National sub-mode.

uint32_t txDataWidth

The width of TX data (valid range 4-16).

It must be the same as rxDataWidth except in National sub-mode.

bool enableMsbFirst

Enables the hardware to shift out the data element MSB first, otherwise, LSB first.

bool enableFreeRunSclk

Enables the master to generate a continuous SCLK regardless of whether there is data to send.

bool enableInputFilter

Enables a digital 3-tap median filter to be applied to the input of the RX FIFO to filter glitches on the line.

bool enableMisoLateSample

Enables the master to sample MISO line one half clock later to allow better timings.

bool enableTransferSeperation

Enables the master to transmit each data element separated by a de-assertion of the slave select line (only applicable for the master mode)

uint32_t ssPolarity

Sets active polarity of each SS line.

This is a bit mask: bit 0 corresponds to SS0 and so on to SS3. 1 means active high, a 0 means active low.

bool ssSetupDelay

Indicates the SPI SELECT setup delay (between SELECT activation and SPI clock).

‘0’: With this setting the same timing is generated as in SCB v1 block. CPHA=0: 0.75 SPI clock cycles CPHA=1: 0.25 SPI clock cycles ‘1’: With this setting an additional delay of 1 SPI clock cycle is generated. CPHA=0: 1.75 SPI clock cycles CPHA=1: 1.25 SPI clock cycles Only applies in SPI MOTOROLA submode and when SCLK_CONTINUOUS=0

note

This parameter is available for CAT1B devices.

bool ssHoldDelay

Indicates the SPI SELECT hold delay (between SPI clock and SELECT deactivation).

‘0’: With this setting the same timing is generated as in CAT1A devices. CPHA=0: 0.75 SPI clock cycles CPHA=1: 0.25 SPI clock cycles ‘1’: With this setting an additional delay of 1 SPI clock cycle is generated. CPHA=0: 1.75 SPI clock cycles CPHA=1: 1.25 SPI clock cycles Only applies in SPI MOTOROLA submode and when SCLK_CONTINUOUS=0

note

This parameter is available for CAT1B devices.

bool ssInterFrameDelay

Indicates the SPI SELECT inter-dataframe delay (between SELECT deactivation and SELECT activation).

‘0’: With this setting the same timing is generated as in CAT1A devices. CPHA=0: 0.75 SPI clock cycles CPHA=1: 0.25 SPI clock cycles ‘1’: With this setting an additional delay of 1 SPI clock cycle is generated. CPHA=0: 1.75 SPI clock cycles CPHA=1: 1.25 SPI clock cycles Only applies in SPI MOTOROLA submode and when SCLK_CONTINUOUS=0

note

This parameter is available for CAT1B devices.

bool enableWakeFromSleep

When set, the slave will wake the device when the slave select line becomes active.

Note that not all SCBs support this mode. Consult the device datasheet to determine which SCBs support wake from Deep Sleep.

uint32_t rxFifoTriggerLevel

When there are more entries in the RX FIFO then this level the RX trigger output goes high.

This output can be connected to a DMA channel through a trigger mux. Also, it controls the CY_SCB_SPI_RX_TRIGGER interrupt source.

uint32_t rxFifoIntEnableMask

Bits set in this mask will allow events to cause an interrupt (See SPI RX FIFO Statuses for the set of constant)

uint32_t txFifoTriggerLevel

When there are fewer entries in the TX FIFO then this level the TX trigger output goes high.

This output can be connected to a DMA channel through a trigger mux. Also, it controls the CY_SCB_SPI_TX_TRIGGER interrupt source.

uint32_t txFifoIntEnableMask

Bits set in this mask allow events to cause an interrupt (See SPI TX FIFO Statuses for the set of constants)

uint32_t masterSlaveIntEnableMask

Bits set in this mask allow events to cause an interrupt (See SPI Master and Slave Statuses for the set of constants)

struct cy_stc_scb_spi_context_t
#include <cy_scb_spi.h>

SPI context structure.

All fields for the context structure are internal. Firmware never reads or writes these values. Firmware allocates the structure and provides the address of the structure to the driver in function calls. Firmware must ensure that the defined instance of this structure remains in scope while the drive is in use.