SPI TX FIFO Statuses

group group_scb_spi_macros_tx_fifo_status

Macros to check SPI TX FIFO status returned by Cy_SCB_SPI_GetTxFifoStatus function or assign mask for Cy_SCB_SPI_ClearTxFifoStatus function.

Each SPI TX FIFO status is encoded in a separate bit, therefore multiple bits may be set to indicate the current status.

Defines

CY_SCB_SPI_TX_TRIGGER

The number of entries in the TX FIFO is less than the TX FIFO trigger level value.

CY_SCB_SPI_TX_NOT_FULL

The TX FIFO is not full, there is a space for more data.

CY_SCB_SPI_TX_EMPTY

The TX FIFO is empty, note that there may still be data in the shift register.

CY_SCB_SPI_TX_OVERFLOW

An attempt to write to the full TX FIFO.

CY_SCB_SPI_TX_UNDERFLOW

Applicable only for the slave mode.

The master tried to read more data elements than available.