SPI TX FIFO Statuses¶
Each SPI TX FIFO status is encoded in a separate bit, therefore multiple bits may be set to indicate the current status.
The number of entries in the TX FIFO is less than the TX FIFO trigger level value.
The TX FIFO is not full, there is a space for more data.
The TX FIFO is empty, note that there may still be data in the shift register.
An attempt to write to the full TX FIFO.
Applicable only for the slave mode.
The master tried to read more data elements than available.