SysClk (System Clock)¶
The System Clock (SysClk) driver contains the API for configuring system and peripheral clocks.
The functions and other declarations used in this driver are in cy_sysclk.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.
Firmware uses the API to configure, enable, or disable a clock.
The clock system includes a variety of resources that can vary per device, including:
Internal clock sources such as internal oscillators
External clock sources such as crystal oscillators or a signal on an I/O pin
Generated clocks such as an FLL, a PLL, and peripheral clocks
Consult the Technical Reference Manual for your device for details of the clock system.
The PDL defines clock system capabilities in:
devices/include/<series>_config.h. (E.g. devices/include/psoc6_01_config.h). User-configurable clock speeds are defined in the file system_<series>.h.
As an illustration of the clocking system, the following diagram shows the PSoC 63 series clock tree. The actual tree may vary depending on the device series. Consult the Technical Reference Manual for your device for details.
The sysclk driver supports multiple peripheral clocks, as well as the fast clock, slow clock, backup domain clock, timer clock, and pump clock. The API for any given clock contains the functions to manage that clock. Functions for clock measurement and trimming are also provided.
The availability of clock functions depend on the availability of the chip resources that support those functions. Consult the device TRM before attempting to use these functions. For PSoC 64 devices the clocks configurations are restricted and limited. Refer to the PRA driver, and the TRM and datasheet for details.PSoC 6 power modes limit the maximum clock frequency. Refer to the SysPm driver and the TRM for details.
On the diagram above, the yellow muxes are glitch-safe. All glitch-safe mux transitions take four cycles of the source clock. It is not allowed to turn off the source clock during that time.
Refer to the technical reference manual (TRM) and the device datasheet.
Reason for Change
Fetch the FLL and PLL frequency.
Support for CM33.
New devices support.
The implementation of Cy_SysClk_ClkPathGetSource, Cy_SysClk_FllConfigure, Cy_SysClk_FllGetConfiguration, Cy_SysClk_PllConfigure and Cy_SysClk_ClkMeasurementCountersGetFreq is updated in accordance to the MISRA 2012 requirements. No behavioral changes.
MISRA 2012 compliance.
Updated source code comments.
Added the assertion mechanism to the following functions:
Now, the functions described above halt in assertion when a PRA request returns not successful operation. This change is applicable only for the PSoC 64 family devices.
Enhancements for the debugging process.
Added Cy_SysClk_PiloInitialTrim and Cy_SysClk_PiloUpdateTrimStep functions. Extended the Cy_SysClk_PiloTrim function to use the step-size value calculated for PILO based on the Cy_SysClk_PiloInitialTrim and Cy_SysClk_PiloUpdateTrimStep functions call.
User experience enhancement.
Added the warning that during a glitch-safe mux, the transition is not allowed to disable the previous clock source. See more info in the Configuration Considerations.
Removed Known Issues table.
Updated SysClk functions for PSoC 64 devices. Now the SysClk functions can return PRA driver status value.
The SysClk driver uses the PRA driver to change the protected registers. A SysClk driver function that calls a PRA driver function will return the PRA error status code if the called PRA function returns an error. In these cases, refer to PRA return statuses. Refer to functions description for details.
Updated the code of Cy_SysClk_ClkPathGetFrequency function.
Make the code more error-resistant to user errors for some corner cases.
Minor documentation updates.
Updated the ECO trimming values calculation algorithm in the Cy_SysClk_EcoConfigure implementation.
This change may invalidate the already used crystals, in cases:
The crystal frequency is less than 16 MHz.
The maximum amplitude (internal calculation value) is less than 0.65 V.
For detail, refer the Cy_SysClk_EcoConfigure documentation and the ECO Trimming section of the device TRM.
Enhanced the ECO performance for high-noise conditions that result from simultaneous switching of GPIOs and/or high switching activity on the chip.
Added the following functions: Cy_SysClk_ExtClkGetFrequency, Cy_SysClk_EcoGetFrequency,
Cy_SysClk_ClkPathMuxGetFrequency, Cy_SysClk_ClkPathGetFrequency, Cy_SysClk_IloIsEnabled.
Cy_SysClk_PiloIsEnabled, Cy_SysClk_AltHfGetFrequency, Cy_SysClk_ClkHfIsEnabled,
Cy_SysClk_ClkTimerIsEnabled, Cy_SysClk_ClkTimerGetFrequency, Cy_SysClk_ClkPumpIsEnabled and
Update documentation based on collateral review feedback.
User experience enhancement.
Fix compiler warning.
Added the following functions: Cy_SysClk_MfoEnable, Cy_SysClk_MfoIsEnabled,
Cy_SysClk_MfoDisable, Cy_SysClk_ClkMfEnable, Cy_SysClk_ClkMfIsEnabled,
Cy_SysClk_ClkMfDisable, Cy_SysClk_ClkMfGetDivider, Cy_SysClk_ClkMfSetDivider,
New device support.
Added the following new API functions Cy_SysClk_FllIsEnabled, Cy_SysClk_PllIsEnabled,
Cy_SysClk_ExtClkSetFrequency, Cy_SysClk_ClkHfGetFrequency, Cy_SysClk_ClkFastGetFrequency,
Cy_SysClk_ClkPeriGetFrequency and Cy_SysClk_ClkSlowGetFrequency
Enhancement based on usability feedback
Deprecated the following macros: CY_SYSCLK_DIV_ROUND and CY_SYSCLK_DIV_ROUNDUP
Macros were moved into SysLib (System Library)
Math library dependency is removed, the floating-point math is replaced with integer math.
Updated the following functions implementation: Cy_SysClk_EcoEnable, Cy_SysClk_EcoGetStatus, Cy_SysClk_FllGetConfiguration
The Cy_SysClk_DeepSleepCallback now implements all four SysPm callback modes cy_en_syspm_callback_mode_t.
The actions that were done in CY_SYSPM_CHECK_READY case are moved to CY_SYSPM_BEFORE_TRANSITION.
So the cy_stc_syspm_callback_t::skipMode must be set to 0UL.
Flattened the organization of the driver source code into the single source directory and the single include directory.
Driver library directory-structure simplification.
Updated Cy_SysClk_FllLocked function description
The SRSS_ver1 HW details clarification
Removed the following functions:
No hardware support for the removed functions.
Added register access layer. Use register access macros instead of direct register access using dereferenced pointers.
Makes register access device-independent, so that the PDL does not need to be recompiled for each supported part number.
Updated the following functions. Now they use a semaphore when try to read the status or configure the SysClk measurement counters:
Now Cy_SysClk_ClkMeasurementCountersGetFreq() returns zero value, if during measurement device was in the Deep Sleep or partially blocking flash operation occurred
Added arbiter mechanism for correct usage of the SysClk measurement counters
Renamed Power Management section to Low Power Callback section
Documentation update and clarification
Updated FLL parameter calculation
Support low frequency sources
Added Cy_SysClk_PiloSetTrim() and Cy_SysclkPiloGetTrim() functions
Support PILO manual trims
Made Cy_SysClk_FllLostLock() function dependent on SRSS v1
Feature is not supported in SRSS v1
Updated Cy_SysClk_DeepSleepCallback() to save/restore both FLL and PLL settings
The function should return when the lock is established or a timeout has occurred
General documentation updates
- General Enumerated Types
- External Clock Source (EXTCLK)
- External Crystal Oscillator (ECO)
- Clock Path Source
- Frequency Locked Loop (FLL)
- Phase Locked Loop (PLL)
- Internal Low-Speed Oscillator (ILO)
- Precision Internal Low-Speed Oscillator (PILO)
- Clock Measurement
- Clock Trim (ILO, PILO)
- Low Power Callback
- Watch Crystal Oscillator (WCO)
- High-Frequency Clocks
- Fast Clock
- Peripheral Clock
- Peripherals Clock Dividers
- Slow Clock
- Alternative High-Frequency Clock
- Low-Frequency Clock
- Timer Clock
- Pump Clock
- Backup Domain Clock
- Medium Frequency Domain Clock