Functions

group group_sysclk_clk_peripheral_funcs

Functions

cy_en_sysclk_status_t Cy_SysClk_PeriphSetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, uint32_t dividerValue)

Sets one of the programmable clock dividers.

This is only used for integer dividers. Use Cy_SysClk_PeriphSetFracDivider for setting factional dividers.

Precondition

If the specified clock divider is already enabled - it should be disabled prior to use this function by Cy_SysClk_PeriphDisableDivider.

Return

cy_en_sysclk_status_t

Function Usage

    /* Scenario: 16-bit peripheral divider #2 needs to be incremented by 1. */

    uint32_t periDiv = Cy_SysClk_PeriphGetDivider(CY_SYSCLK_DIV_16_BIT, 2UL);
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 2UL, periDiv + 1UL);

Parameters
  • dividerType: specifies which type of divider to use; cy_en_divider_types_t

  • dividerNum: the divider number.

  • dividerValue: divider value Causes integer division of (divider value + 1), or division by 1 to 256 (8-bit divider) or 1 to 65536 (16-bit divider).

uint32_t Cy_SysClk_PeriphGetDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum)

Returns the integer divider value for the specified divider.

One works for integer dividers. Use Cy_SysClk_PeriphGetFracDivider to get the fractional divider value

Return

The divider value. The integer division done is by (divider value + 1), or division by 1 to 256 (8-bit divider) or 1 to 65536 (16-bit divider).

Function Usage

    /* Scenario: 16-bit peripheral divider #2 needs to be incremented by 1. */

    uint32_t periDiv = Cy_SysClk_PeriphGetDivider(CY_SYSCLK_DIV_16_BIT, 2UL);
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 2UL, periDiv + 1UL);

Parameters
  • dividerType: specifies which type of divider to use; cy_en_divider_types_t

  • dividerNum: specifies which divider of the selected type to configure

cy_en_sysclk_status_t Cy_SysClk_PeriphSetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, uint32_t dividerIntValue, uint32_t dividerFracValue)

Sets one of the programmable clock dividers.

This function should only be used for fractional clock dividers.

Precondition

If the specified clock divider is already enabled - it should be disabled prior to use this function by Cy_SysClk_PeriphDisableDivider.

Return

cy_en_sysclk_status_t

Function Usage

    /* Scenario: 16-bit fractional peripheral divider #0 needs to increment its
                 fractional value by 2. */

    uint32_t divIntVal, divFracVal;

    Cy_SysClk_PeriphGetFracDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL, &divIntVal, &divFracVal);
    (void)Cy_SysClk_PeriphSetFracDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL, divIntVal, divFracVal + 2UL);

Parameters
  • dividerType: specifies which type of divider to use; cy_en_divider_types_t

  • dividerNum: specifies which divider of the selected type to configure

  • dividerIntValue: the integer divider value The source of the divider is peri_clk, which is a divided version of hf_clk[0]. The divider value causes integer division of (divider value + 1), or division by 1 to 65536 (16-bit divider) or 1 to 16777216 (24-bit divider).

  • dividerFracValue: the fraction part of the divider The fractional divider can be 1-32, thus it divides the clock by 1/32 for each count. To divide the clock by 11/32nds set this value to 11.

void Cy_SysClk_PeriphGetFracDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, uint32_t *dividerIntValue, uint32_t *dividerFracValue)

Reports the integer and fractional parts of the divider.

Return

None. Loads pointed-to variables.

Function Usage

    /* Scenario: 16-bit fractional peripheral divider #0 needs to increment its
                 fractional value by 2. */

    uint32_t divIntVal, divFracVal;

    Cy_SysClk_PeriphGetFracDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL, &divIntVal, &divFracVal);
    (void)Cy_SysClk_PeriphSetFracDivider(CY_SYSCLK_DIV_16_5_BIT, 0UL, divIntVal, divFracVal + 2UL);

Parameters
  • dividerType: specifies which type of divider to use; cy_en_divider_types_t

  • dividerNum: specifies which divider of the selected type to configure

  • *dividerIntValue: pointer to return integer divider value

  • *dividerFracValue: pointer to return fractional divider value

cy_en_sysclk_status_t Cy_SysClk_PeriphAssignDivider(en_clk_dst_t ipBlock, cy_en_divider_types_t dividerType, uint32_t dividerNum)

Assigns a programmable divider to a selected IP block, such as a TCPWM or SCB.

Return

cy_en_sysclk_status_t

Function Usage

    /* Scenario: The source of TCPWM0 CNT0 clock needs to be known. If this
                 source is not 16-bit divider #3, update it to be sourced from
                 that clock divider and set the divider value to 2000. */

    uint32_t currDiv    = Cy_SysClk_PeriphGetAssignedDivider(PCLK_TCPWM0_CLOCKS0);
    uint32_t newDiv     = _VAL2FLD(PERI_DIV_CMD_TYPE_SEL, CY_SYSCLK_DIV_16_BIT)
                            | _VAL2FLD(PERI_DIV_CMD_DIV_SEL, 3UL);
    if(currDiv != newDiv)
    {
        /* Assign 16-bit divider #3 to source TCPWM0 CNT0 clock */
        (void)Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS0, CY_SYSCLK_DIV_16_BIT, 3UL);
    }

    /* Set the 16-bit divider #3 value to 2000 (1999 + 1) */
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 3UL, 1999UL);

    /* Enable the 16-bit divider #3 */
    (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 3UL);

Parameters
  • ipBlock: specifies ip block to connect the clock divider to.

  • dividerType: specifies which type of divider to use; cy_en_divider_types_t

  • dividerNum: specifies which divider of the selected type to configure

uint32_t Cy_SysClk_PeriphGetAssignedDivider(en_clk_dst_t ipBlock)

Reports which clock divider is assigned to a selected IP block.

Return

The divider type and number, where bits [7:6] = type, bits[5:0] = divider number within that type

Function Usage

    /* Scenario: The source of TCPWM0 CNT0 clock needs to be known. If this
                 source is not 16-bit divider #3, update it to be sourced from
                 that clock divider and set the divider value to 2000. */

    uint32_t currDiv    = Cy_SysClk_PeriphGetAssignedDivider(PCLK_TCPWM0_CLOCKS0);
    uint32_t newDiv     = _VAL2FLD(PERI_DIV_CMD_TYPE_SEL, CY_SYSCLK_DIV_16_BIT)
                            | _VAL2FLD(PERI_DIV_CMD_DIV_SEL, 3UL);
    if(currDiv != newDiv)
    {
        /* Assign 16-bit divider #3 to source TCPWM0 CNT0 clock */
        (void)Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS0, CY_SYSCLK_DIV_16_BIT, 3UL);
    }

    /* Set the 16-bit divider #3 value to 2000 (1999 + 1) */
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 3UL, 1999UL);

    /* Enable the 16-bit divider #3 */
    (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 3UL);

Parameters
  • ipBlock: specifies ip block to connect the clock divider to.

cy_en_sysclk_status_t Cy_SysClk_PeriphEnableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum)

Enables the selected divider.

note

This function also sets the phase alignment bits such that the enabled divider is aligned to clk_peri. See Cy_SysClk_PeriphDisableDivider() for information on how to phase-align a divider after it is enabled.

Function Usage

    /* Scenario: TCPWM0 CNT0 clock needs to be sourced from 8-bit divider #1 with
                 a value of 140. This clock must be aligned to Peri clock. */

    /* Assign 8-bit divider #1 to source TCPWM0 CNT0 clock */
    (void)Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCKS0, CY_SYSCLK_DIV_8_BIT, 1UL);

    /* Set the 8-bit divider #1 value to 140 (139 + 1) */
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1UL, 139UL);

    /* Enable the 8-bit divider #1 */
    (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1UL);

Parameters
  • dividerType: specifies which type of divider to use; cy_en_divider_types_t

  • dividerNum: specifies which divider of the selected type to configure

cy_en_sysclk_status_t Cy_SysClk_PeriphDisableDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum)

Disables a selected divider.

Function Usage

    /* Scenario: 8-bit divider #1 is no longer needed and can be disabled. */
    (void)Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1UL);

Parameters
  • dividerType: specifies which type of divider to use; cy_en_divider_types_t.

  • dividerNum: specifies which divider of the selected type to configure.

cy_en_sysclk_status_t Cy_SysClk_PeriphEnablePhaseAlignDivider(cy_en_divider_types_t dividerType, uint32_t dividerNum, cy_en_divider_types_t dividerTypePA, uint32_t dividerNumPA)

First disables a selected divider (Cy_SysClk_PeriphDisableDivider), then aligns that divider to another programmable divider, and enables the selected divider.

The divider to align to must already be enabled in order to align a divider to it.

note

To phase-align a divider to clk_peri, set dividerTypePA to 3 and dividerNumPA to 63.

Function Usage

    /* Scenario: 8-bit divider #1 needs to be aligned to 16-bit divider #0. */

    /* Set the 8-bit divider #1 value to 125 (124 + 1) */
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1UL, 124UL);
    (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1UL);

    /* Set the 16-bit divider #0 value to 2000 (1999 + 1) */
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_16_BIT, 0UL, 1999UL);
    (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0UL);

    /* Align the 8-bit divider #1 to the 16-bit divider #0 */
    (void)Cy_SysClk_PeriphEnablePhaseAlignDivider(CY_SYSCLK_DIV_8_BIT, 1UL, CY_SYSCLK_DIV_16_BIT, 0UL);

Parameters
  • dividerType: specifies which type of divider to use; cy_en_divider_types_t.

  • dividerNum: specifies which divider of the selected type to configure.

  • dividerTypePA: type of divider to phase-align to; cy_en_divider_types_t.

  • dividerNumPA: divider number of type specified to phase align to.

bool Cy_SysClk_PeriphGetDividerEnabled(cy_en_divider_types_t dividerType, uint32_t dividerNum)

Reports the enabled/disabled atate of the selected divider.

Return

The enabled/disabled state;

false = disabled

true = enabled

Function Usage

    /* Scenario: Check if the 16-bit divider #0 is enabled. If it is not, then
                 enable the divider. */

    if(true == Cy_SysClk_PeriphGetDividerEnabled(CY_SYSCLK_DIV_16_BIT, 0UL))
    {
        (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_16_BIT, 0UL);
    }

Parameters
  • dividerType: specifies which type of divider to use; cy_en_divider_types_t.

  • dividerNum: specifies which divider of the selected type to configure.

uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_t dividerNum)

Reports the frequency of the output of a given peripheral divider.

note

The reported frequency may be zero, which indicates unknown. This happens if the source input is dsi_out or clk_altlf.

Return

The frequency, in Hz.

Function Usage

    /* Scenario: SCB0 needs to be clocked at PeriClk/3. Need to confirm that the
                 set frequency on the chosen peripheral divider is correct.
                 HFCLK0 and the clocks leading up it are configured. */

    /* Set the Peri clock divider to 2 (1 + 1) */
    Cy_SysClk_ClkPeriSetDivider(1U);

    /* Assign 8-bit divider #0 to source SCB0 clock */
    (void)Cy_SysClk_PeriphAssignDivider(PCLK_SCB0_CLOCK, CY_SYSCLK_DIV_8_BIT, 0UL);

    /* Set the 8-bit divider #0 value to 3 (2 + 1) */
    (void)Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0UL, 2UL);

    /* Enable the 8-bit divider #0 */
    (void)Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0UL);

    /* Calculate the frequency seen at the output of 8-bit divider #0 */
    uint32_t scbFreq = Cy_SysClk_PeriphGetFrequency(CY_SYSCLK_DIV_8_BIT, 0UL);

    if(scbFreq == 0UL)
    {
        /* Could not calculate the frequency. Check that the clock source
           is correct and/or verify by enabling the SCB0. */
    }
    else
    {
        /* Check that the frequency is as expected. */
    }

Parameters
  • dividerType: specifies which type of divider to use; cy_en_divider_types_t

  • dividerNum: specifies which divider of the selected type to configure