Slow Clock

group group_sysclk_clk_slow

The slow clock is the source clock for the “slow” processor (e.g.

Cortex-M0+ in PSoC 6). This clock is a divided version of the Peripheral Clock, which in turn is a divided version of CLK_HF0. A divider value of 1~256 can be used to further divide the Peri clock to a desired clock speed for the processor.

../../../_images/sysclk_slow.png

API Reference