Functions

group group_sysclk_clk_slow_funcs

Functions

void Cy_SysClk_ClkSlowSetDivider(uint8_t divider)

Sets the clock divider for the slow clock.

The source of this clock is the peripheral clock (clkPeri), which is sourced from clkHf[0].

note

Call SystemCoreClockUpdate after this function calling.

Function Usage

    /* Scenario: HFCLK0 is configured and enabled. The Slow clock sourcing the
                 CM0+ core must run at a frequency that is 1/32 of HFCLK0. */

    /* Slow clock is sourced from Peri clock. Set the divider to 1 (freq = HFCLK0) */
    Cy_SysClk_ClkPeriSetDivider(1u);

    if(32u != Cy_SysClk_ClkSlowGetDivider())
    {
        Cy_SysClk_ClkSlowSetDivider(32u);
    }

    /* Get the CM0+ clock source frequency */
    uint32_t clkSlowfreq = Cy_SysClk_ClkSlowGetFrequency();

Parameters
  • divider: Divider value between 0 and 255. Causes integer division of (divider value + 1), or division by 1 to 256.

uint8_t Cy_SysClk_ClkSlowGetDivider(void)

Reports the divider value for the slow clock.

Return

The divider value. The integer division done is by (divider value + 1), or division by 1 to 256.

Function Usage

    /* Scenario: HFCLK0 is configured and enabled. The Slow clock sourcing the
                 CM0+ core must run at a frequency that is 1/32 of HFCLK0. */

    /* Slow clock is sourced from Peri clock. Set the divider to 1 (freq = HFCLK0) */
    Cy_SysClk_ClkPeriSetDivider(1u);

    if(32u != Cy_SysClk_ClkSlowGetDivider())
    {
        Cy_SysClk_ClkSlowSetDivider(32u);
    }

    /* Get the CM0+ clock source frequency */
    uint32_t clkSlowfreq = Cy_SysClk_ClkSlowGetFrequency();

uint32_t Cy_SysClk_ClkSlowGetFrequency(void)

Reports the frequency of the slow clock.

Return

The frequency, in Hz.

Function Usage

    /* Scenario: HFCLK0 is configured and enabled. The Slow clock sourcing the
                 CM0+ core must run at a frequency that is 1/32 of HFCLK0. */

    /* Slow clock is sourced from Peri clock. Set the divider to 1 (freq = HFCLK0) */
    Cy_SysClk_ClkPeriSetDivider(1u);

    if(32u != Cy_SysClk_ClkSlowGetDivider())
    {
        Cy_SysClk_ClkSlowSetDivider(32u);
    }

    /* Get the CM0+ clock source frequency */
    uint32_t clkSlowfreq = Cy_SysClk_ClkSlowGetFrequency();