Frequency Locked Loop (FLL)¶
The FLL is a clock generation circuit that can be used to produce a higher frequency clock from a reference clock.
The output clock exhibits some characteristics of the reference clock such as the accuracy of the source. However other attributes such as the clock phase are not preserved. The FLL is similar in purpose to a (Phase locked loop) PLL but they are not equivalent.
They may have different frequency ranges.
The FLL starts up (locks) faster and consumes less current than the PLL.
The FLL accepts a source clock with lower frequency than PLL, such as the WCO (32 KHz).
The FLL does not lock phase. The hardware consist of a counter with a current-controlled oscillator (CCO). The counter counts the number of output clock edges in a reference clock period and adjusts the CCO until the expected ratio is achieved (locked). After initial lock, the CCO is adjusted dynamically to keep the ratio within tolerance. The lock tolerance is user-adjustable.
The SysClk driver supports two models for configuring the FLL. The first model is to call the Cy_SysClk_FllConfigure() function, which calculates the necessary parameters for the FLL at run-time. This may be necessary for dynamic run-time changes to the FLL. However this method is slow as it needs to perform the calculation before configuring the FLL. The other model is to call Cy_SysClk_FllManualConfigure() function with pre-calculated parameter values. This method is faster but requires prior knowledge of the necessary parameters. Consult the device TRM for the FLL calculation equations.