Functions

group group_sysclk_fll_funcs

Functions

cy_en_sysclk_status_t Cy_SysClk_FllConfigure(uint32_t inputFreq, uint32_t outputFreq, cy_en_fll_pll_output_mode_t outputMode)

Configures the FLL, for best accuracy optimization.

note

Call this function after changing the FLL input frequency, for example if Cy_SysClk_ClkPathSetSource() is called.

note

Do not call this function when the FLL is enabled. If it is called, then this function returns with an CY_SYSCLK_INVALID_STATE return value and no register updates.

note

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

note

Call Cy_SysLib_SetWaitStates before calling this function if the FLL is the source of CLK_HF0 and the FLL frequency is increasing.

note

Call Cy_SysLib_SetWaitStates after calling this function if the FLL is the source of CLK_HF0 and the FLL frequency is decreasing.

note

On PSoC 64 devices the configuration on the PRA driver will be reflected after Cy_SysClk_FllEnable call. Any call to Cy_SysClk_FllGetConfiguration before calling Cy_SysClk_FllEnable returns old configuration values.

Return

Error / status code:

CY_SYSCLK_SUCCESS - FLL successfully configured

CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled

CY_SYSCLK_BAD_PARAM - desired output frequency is out of valid range

Function Usage

    /* Scenario: FLL needs to source HFCLK0, which must operate at 100 MHz.
                 The IMO sources the FLL at 8MHz. Startup time is not an issue
                 and manual configuration of the FLL is not needed. */

    /* Set the FLL source (path 0 mux) to be the IMO */
    (void)Cy_SysClk_ClkPathSetSource(0UL, CY_SYSCLK_CLKPATH_IN_IMO);

    /* Auto-configure the FLL */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllConfigure(CY_SYSCLK_IMO_FREQ,               /* Input clock = 8 MHz */
                                                    100000000UL,                      /* Output clock = 100 MHz */
                                                    CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT))  /* Bypass Mux to FLL Output */
    {
        /* Insert error handling */
    }

    /* Enable the FLL with 2000 microsecond timeout */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(2000UL))
    {
        /* Insert error handling */
    }

    /* Set the HFCLK0 source to clock path 0 */
    (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);

Parameters
  • inputFreq: frequency of input source, in Hz

  • outputFreq: Desired FLL output frequency, in Hz. Allowable range is 24 MHz to 100 MHz. In all cases, FLL_OUTPUT_DIV must be set; the output divide by 2 option is required.

  • outputMode: cy_en_fll_pll_output_mode_t If output mode is bypass, then the output frequency equals the input source frequency regardless of the frequency parameter values.

cy_en_sysclk_status_t Cy_SysClk_FllManualConfigure(const cy_stc_fll_manual_config_t *config)

Manually configures the FLL based on user inputs.

note

Call this function after changing the FLL input frequency, for example if Cy_SysClk_ClkPathSetSource() is called.

note

Do not call this function when the FLL is enabled. If it is called, then this function returns immediately with an CY_SYSCLK_INVALID_STATE return value and no register updates.

note

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

note

Call Cy_SysLib_SetWaitStates before calling this function if the FLL is the source of CLK_HF0 and the FLL frequency is increasing.

note

Call Cy_SysLib_SetWaitStates after calling this function if the FLL is the source of CLK_HF0 and the FLL frequency is decreasing.

note

On PSoC 64 devices the configuration on the PRA driver will be reflected after Cy_SysClk_FllEnable call. Any call to Cy_SysClk_FllGetConfiguration before calling Cy_SysClk_FllEnable returns old configuration values.

Return

Error / status code:

CY_SYSCLK_SUCCESS - FLL successfully configured

CY_SYSCLK_INVALID_STATE - FLL not configured because it is enabled CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to

cy_en_pra_status_t for more details.

Function Usage

    /* Scenario: FLL needs to source HFCLK0, which must operate at 100 MHz.
                 The IMO sources the FLL at 8MHz. The characteristics of the
                 FLL lock parameters are already known and the startup time
                 for the FLL configuration must be minimized. */

    /* Refer to the TRM for the full set of equations used to calculate the parameters */
    const cy_stc_fll_manual_config_t fllConfig =
    {
        /*.fllMult =*/         1725UL,                        /* Multiplier for CCO frequency */
        /*.refDiv =*/          (uint16_t)69u,                 /* Reference clock divider */
        /*.ccoRange =*/        CY_SYSCLK_FLL_CCO_RANGE4,      /* Target CCO range of 200 (100*2) MHz */
        /*.enableOutputDiv =*/ true,                          /* Output divider enabled (divide by 2) */
        /*.lockTolerance =*/   33u,                           /* Lock tolerance */
        /*.igain =*/           7u,                            /* FLL loop filter integral gain */
        /*.pgain =*/           5u,                            /* FLL loop filter proportional gain */
        /*.settlingCount =*/   8u,                            /* Wait count before loop measurement restarts */
        /*.outputMode =*/      CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT,/* Bypass Mux to FLL Output */
        /*.cco_Freq =*/        355u                           /* CCO frequency code (HW controlled during lock) */
    };

    /* Set the FLL source (path 0 mux) to be the IMO */
    (void)Cy_SysClk_ClkPathSetSource(0UL, CY_SYSCLK_CLKPATH_IN_IMO);

    /* Configure the FLL lock using pre-calculated values */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllManualConfigure(&fllConfig))
    {
        /* Insert error handling */
    }

    /* Enable the FLL with 2000 microsecond timeout */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllEnable(2000UL))
    {
        /* Insert error handling */
    }

    /* Set the HFCLK0 source to clock path 0 */
    (void)Cy_SysClk_ClkHfSetSource(0UL, CY_SYSCLK_CLKHF_IN_CLKPATH0);

Parameters

void Cy_SysClk_FllGetConfiguration(cy_stc_fll_manual_config_t *config)

Reports the FLL configuration settings.

note

On PSoC 64 devices the configuration on the PRA driver will be reflected after Cy_SysClk_FllEnable call. Any call to Cy_SysClk_FllGetConfiguration before calling Cy_SysClk_FllEnable returns old configuration values.

Function Usage

    /* Scenario: The calculated FLL parameters need to be checked. */

    cy_stc_fll_manual_config_t fllConfig;

    /* Auto-configure the FLL */
    if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllConfigure(8000000UL,                        /* Input clock = 8 MHz */
                                                    100000000UL,                      /* Output clock = 100 MHz */
                                                    CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT))  /* Bypass Mux to FLL Output */
    {
        /* Insert error handling */
    }

    /* Retrieve the calculated parameters */
    Cy_SysClk_FllGetConfiguration(&fllConfig);

Parameters

cy_en_sysclk_status_t Cy_SysClk_FllEnable(uint32_t timeoutus)

Enables the FLL.

The FLL should be configured before calling this function.

note

While waiting for the FLL to lock, the FLL bypass mode is set to CY_SYSCLK_FLLPLL_OUTPUT_INPUT. After the FLL is locked, the FLL bypass mdoe is then set to CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT.

note

Call SystemCoreClockUpdate after calling this function if it affects the CLK_HF0 frequency.

note

Call Cy_SysLib_SetWaitStates before calling this function if the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is increasing.

Return

Error / status code:

CY_SYSCLK_SUCCESS - FLL successfully enabled

CY_SYSCLK_TIMEOUT - Timeout waiting for FLL lock CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to

cy_en_pra_status_t for more details.

Function Usage

    /* Scenario: FLL is configured and needs to be enabled within 2 ms */

    #define CLKPATH0 (0UL)

    uint32_t clkPathFreq = 0UL; /* Variable to store the Clock Path output frequency */

    /* Enable the FLL with a timeout of 2000 microseconds */
    if (CY_SYSCLK_SUCCESS == Cy_SysClk_FllEnable(2000UL))
    {
        clkPathFreq = Cy_SysClk_ClkPathGetFrequency(CLKPATH0);
        /* Now clkPathFreq contains an actual FLL frequency */
    }
    else
    {
        /* Insert error handling */
    }

Parameters
  • timeoutus: Amount of time in micro seconds to wait for FLL to lock. If lock doesn’t occur, the FLL is stopped. To avoid waiting for lock, set this to 0 and manually check for lock using Cy_SysClk_FllLocked.

bool Cy_SysClk_FllIsEnabled(void)

Reports whether or not the FLL is enabled.

Return

false = disabled

true = enabled

Function Usage

    /* Scenario: FLL failed to enable and must be reconfigured. Or the FLL is no
                 longer used and hence needs to be disabled. */

    if (Cy_SysClk_FllIsEnabled())
    {
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllDisable())
        {
            /* Insert error handling */
        }
    }

    /* The clocks that relied on the FLL will now run off of the clock that
       was used to source the FLL (e.g. IMO or ECO). */

bool Cy_SysClk_FllLocked(void)

Reports whether the FLL is locked first time during FLL starting.

Intended to be used with Cy_SysClk_FllEnable with zero timeout.

note

The unlock occurrence may appear during FLL normal operation, so this function is not recommended to check the FLL normal operation stability.

Return

false = not locked

true = locked

Function Usage

    /* Scenario: FLL is configured and needs to be enabled in a non-blocking way */

    /* Enable the FLL without timeout */
    (void)Cy_SysClk_FllEnable(0UL);

    /* Check the status of the lock */
    while(!Cy_SysClk_FllLocked())
    {
        /* Perform other actions while the FLL is locking */
    }

    /* FLL Locked. Proceed with further configuration */

cy_en_sysclk_status_t Cy_SysClk_FllDisable(void)

Disables the FLL and the CCO.

note

Call SystemCoreClockUpdate after this function calling if it affects the CLK_HF0 frequency.

note

Call Cy_SysLib_SetWaitStates after calling this function if the FLL is the source of CLK_HF0 and the CLK_HF0 frequency is decreasing.

Return

cy_en_sysclk_status_t CY_SYSCLK_INVALID_STATE - ECO already enabled For the PSoC 64 devices there are possible situations when function returns the PRA error status code. This is because for PSoC 64 devices the function uses the PRA driver to change the protected registers. Refer to cy_en_pra_status_t for more details.

Function Usage

    /* Scenario: FLL failed to enable and must be reconfigured. Or the FLL is no
                 longer used and hence needs to be disabled. */

    if (Cy_SysClk_FllIsEnabled())
    {
        if (CY_SYSCLK_SUCCESS != Cy_SysClk_FllDisable())
        {
            /* Insert error handling */
        }
    }

    /* The clocks that relied on the FLL will now run off of the clock that
       was used to source the FLL (e.g. IMO or ECO). */

uint32_t Cy_SysClk_FllGetFrequency(void)

Returns the output frequency of the FLL.

note

If the return value equals zero, that means FLL is disabled.

Return

The output frequency of FLL.

Function Usage

    uint32_t freq = Cy_SysClk_FllGetFrequency();
    (void) freq; /* Supress 'unused variable' warning */